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? freescale semiconductor, inc., 2005?2008. all rights reserved. freescale semiconductor data sheet: technical data this document contains information on a new product. specificatio ns and information herein are su bject to change without notice . document number: mcimx31 rev. 4.1, 11/2008 mcimx31 and mcimx31l package information plastic package case 1581 14 x 14 mm, 0.5 mm pitch case 1931 19 x 19 mm, 0.8 mm pitch ordering information see ta bl e 1 on page 3 for ordering information. 1 introduction the mcimx31 and mcimx31l multimedia applications processors represent the next step in low-power, high-performan ce application processors. unless otherwise specified, the ma terial in this data sheet is applicable to both the mcimx31 and mcimx31l processors and referred to singularly throughout this document as mcimx31. the mcimx31l does not include a graphics processing unit (gpu). based on an arm11? micr oprocessor core, the mcimx31 provides the performance with low power consumption required by modern digital devices such as: ? feature-rich cellular phones ? portable media player s and mobile gaming machines ? personal digital assistants (pdas) and wireless pdas ? portable dvd players ? digital cameras the mcimx31 takes advantage of the arm1136jf-s? core running at up to 532 mhz, and is optimized for mcimx31 and mcimx31l multimedia applications processors contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ordering information . . . . . . . . . . . . . . . . . . . . . 3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . 4 functional description and application information . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 arm11 microprocessor core . . . . . . . . . . . . . . 4 module inventory . . . . . . . . . . . . . . . . . . . . . . . 6 signal descriptions . . . . . . . . . . . . . . . . . . . . . . 9 electrical characteristics . . . . . . . . . . . . . . . . 10 chip-level conditions . . . . . . . . . . . . . . . . . . 10 supply power-up/power-down requirements and restrictions . . . . . . . . . . . . . . . . . . . . 18 module-level electrical specifications . . . . . . 21 package information and pinout . . . . . . . . . 104 mapbga production package? 457 14 x 14 mm, 0.5 mm pitch . . . . . . . . . . . 104 mapbga production package? 473 19 x 19 mm, 0.8 mm pitch . . . . . . . . . . . 110 ball maps . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 product differences . . . . . . . . . . . . . . . . . . . . 118 product documentation . . . . . . . . . . . . . . . . 119 revision history . . . . . . . . . . . . . . . . . . . . . . . 120
mcimx31/mcimx31l technical data, rev. 4.1 2 freescale semiconductor introduction minimal power consumption using th e most advanced techniques for po wer saving (dptc, dvfs, power gating, clock gating). with 90 nm technology and dual-vt tra nsistors (two threshold voltages), the mcimx31 provides the optimal performance versus leakage current balance. the performance of the mcimx31 is boosted by a multi-level cache system , and features peripheral devices such as an mpeg-4 hard ware encoder (vga, 30 fps), an au tonomous image processing unit, a vector floating point (vfp11) co-process or, and a risc-based sdma controller. the mcimx31 supports connections to various types of external memo ries, such as ddr, nand flash, nor flash, sdram, and sram. the mcimx31 can be co nnected to a variety of external devices using technology, such as high-speed usb2.0 ot g, ata, mmc/sdio, and compact flash. 1.1 features the mcimx31 is designed for the high-tier, mid-tier smartphone markets, and portable media players. they provide low-power solutions for high-pe rformance demanding multimedia and graphics applications. the mcimx31 is built around the arm11 mcu core and implemented in the 90 nm technology. the systems include the following features: ? multimedia and floating-point hardware acceleration supporting: ? mpeg-4 real-time encode of up to vga at 30 fps ? mpeg-4 real-time video post-pr ocessing of up to vga at 30 fps ? video conference call of up to qcif-30 fps (decoder in software), 128 kbps ? video streaming (playback) of up to vga-30 fps, 384 kbps ? 3d graphics and other applicat ions acceleration with the arm ? tightly-coupled vector floating point co-processor ? on-the-fly video processing that reduces sy stem memory load (for example, the power-efficient viewfinder application with no invo lvement of either the memory system or the arm cpu) ? advanced power management ? dynamic voltage and frequency scaling ? multiple clock and power domains ? independent gating of power domains ? multiple communication and expansion ports includi ng a fast parallel interface to an external graphic accelerator (supporting majo r graphic accelerator vendors) ? security
introduction mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 3 1.2 ordering information table 1 provides the ordering information for the mcimx31. 1.2.1 feature differences between mask sets the following is a summary of di fferences between silicon revision 2.0, mask set m91e, and previous revisions of silicon. a complete list of these differences is given in table 72 . ? extended operating temperatur e range is available: ?40 c to 85 c ? supply current information changes, as shown in table 13 and table 14 ? fuse_vdd supply voltage is floate d or grounded during read operation ? no restriction on pll vers us core supply voltage ? operating frequency as shown in table 8 . table 1. ordering information part number silicon revision 1, 2, 3,4 1 information on reading the silicon revision register can be found in the ic identification (iim) chapter of the reference manua l, see section 7, ?product documentation .? 2 errata and fix information of the various mask sets can be found in the standard mcimx31 chip errata, see section 7, ?product documentation .? 3 changes in output buffer characteristics can be found in the i/ o setting exceptions and special pad descriptions table in the reference manual, see section 7, ?product documentation .? 4 jtag functionality is not tested nor guaranteed at -40c. device mask operating temperature range ( c) package 5 5 case 1581 and 1931 are rohs compliant, lead-free, msl = 3, and solders at 260 c. mcimx31vkn5 1.15 2l38w and 3l38w 0 to 70 14 x 14 mm, 0.5 mm pitch, mapbga-457, case 1581 mcimx31lvkn5 1.15 2l38w and 3l38w 0 to 70 mcimx31vkn5b 1.2 m45g 0 to 70 mcimx31lvkn5b 1.2 m45g 0 to 70 mcimx31vkn5c 2.0 m91e 0 to 70 14 x 14 mm, 0.5 mm pitch, mapbga-457, case 1581 mcimx31lvkn5c 2.0 m91e 0 to 70 mcimx31cvkn5c 2.0 m91e ?40 to 85 mcimx31lcvkn5c 2.0 m91e ?40 to 85 MCIMX31VMN5C 2.0 m91e 0 to 70 19 x 19 mm, 0.8 mm pitch, case 1931 mcimx31lvmn5c 2.0 m91e 0 to 70
mcimx31/mcimx31l technical data, rev. 4.1 4 freescale semiconductor functional description and application information 1.3 block diagram figure 1 shows the mcimx31 simplified interface block diagram. figure 1. mcimx31 simplified interface block diagram 2 functional description and application information 2.1 arm11 microprocessor core the cpu of the mcimx31 is the arm1136jf-s core b ased on the arm v6 architect ure. it supports the arm thumb ? instruction sets, features jazelle ? technology (which enables di rect execution of java byte codes), and a range of simd dsp instructions that opera te on 16-bit or 8-bit data values in 32-bit registers. the arm1136jf-s processor core features: ? integer unit with integral embeddedice ? logic ? eight-stage pipeline ? branch prediction with return stack ? low-interrupt latency external memory ap peripherals sram, psram, sdram nand flash, smartmedia gpu * camera mpeg-4 baseband sd card fast irda usb image processing unit (ipu) parallel sensor (2) serial lcd timers audmux ssi (2) uart (5) gpt pwm epit (2) rtc gpio wdog 1-wire ? cspi (3) i 2 c (3) fir kpp ccm arm11 tm platform i-cache d-cache l2-cache rompatch vfp sdma usb-otg iim expansion sim ata pcmcia/cf mem stick (2) sdhc (2) usb host (2) * gpu unavailable for i.mx31l inversion and rotation camera interface blending display/tv ctl pre and post processing display (2) nor flash ddr wlan bluetooth interface (emi) power management ic pc card pc card host/device mouse keyboard ta m p e r detection serial eprom video encoder 8 x 8 keypad gps ata hard drive arm1136jf-s tm max memory internal security rnga scc rtic debug ect sjc etm
functional description and application information mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 5 ? instruction and data memory management units (mmus), managed usin g micro tlb structures backed by a unified main tlb ? instruction and data l1 c aches, including a non-blocking da ta cache with hit-under-miss ? virtually indexed/physi cally addressed l1 caches ? 64-bit interface to both l1 caches ? write buffer (bypassable) ? high-speed advanced micr o bus architecture (amba) ? l2 interface ? vector floating point co-processor (vfp) for 3d graphics and other floati ng-point applications hardware acceleration ? etm ? and jtag-based debug support 2.1.1 memory system the arm1136jf-s complex includes 16 kb instruction a nd 16 kb data l1 caches. it connects to the mcimx31 l2 unified cache through 64-bit instruction (rea d-only), 64-bit data read/w rite (bi-directional), and 64-bit data write interfaces. the embedded 16k sram can be used for audio str eaming data to avoid external memory accesses for the low-power audio playback, for security, or for other applicati ons. there is also a 32-kb rom for bootstrap code and other fre quently-used code and data. a rom patch module provides the ability to patch the inte rnal rom. it can also initiate an external boot by overriding the boot reset sequence by a jump to a configurable address. table 2 shows information about the mcimx31 core in tabular form. table 2. mcimx31 core core acronym core name brief description integrated memory includes arm11 or arm1136 arm1136 platform the arm1136? platform consists of the arm1136jf-s core, the etm real-time debug modules, a 6 x 5 multi-layer ahb crossbar switch (max), and a vector floating processor (vfp). the mcimx31 provides a high-performance arm11 microprocessor core and highly integrated system functions. th e arm application processor (ap) and other subsystems address the needs of the personal, wireless, and portable product market with integrated peripherals, advanced processor core, and power management capabilities. ? 16 kbyte instruction cache ? 16 kbyte data cache ? 128 kbyte l2 cache ? 32 kbyte rom ? 16 kbyte ram
mcimx31/mcimx31l technical data, rev. 4.1 6 freescale semiconductor functional description and application information 2.2 module inventory table 3 shows an alphabetical listing of the modules in the multimedia appl ications processor. for extended descriptions of the modules, see the reference manual. a cros s-reference is provided to the electrical specifications and timing information fo r each module with extern al signal connections. table 3. digital and analog modules block mnemonic block name functional grouping brief description section/ page 1-wire? 1-wire interface connectivity peripheral the 1-wire module provides bi-directional communication between the arm11 core and external 1-wire devices. 4.3.4/26 ata advanced technology (at) attachment connectivity peripheral the ata block is an at attachment host interface. it is designed to interface with ide hard disc drives and atapi optical disc drives. 4.3.5/27 audmux digital audio multiplexer multimedia peripheral the audmux interconnections allow multiple, simultaneous audio/voice/data flows between th e ports in point-to-point or point-to-multipoint configurations. 4.3.6/36 camp clock amplifier module clock the camp converts a square wave/sinusoidal input into a rail-to-rail square wave. the output of camp feeds the predivider. 4.3.3/25 ccm clock control module clock the ccm provides clock, reset, and power management control for the mcimx31. ? cspi configurable serial peripheral interface (x 3) connectivity peripheral the cspi is equipped with data fifos and is a master/slave configurable serial peripheral interface module, capable of interfacing to both spi master and slave devices. 4.3.7/36 dpll digital phase lock loop clock the dplls produce high-frequency on-chip clocks with low frequency and phase jitters. note: external clock sources provide the reference frequencies. 4.3.8/37 ect embedded cross trigger debug the ect is composed of three ctis (cross trigger interface) and one ctm (cross trigger matrix?key in the multi-core and multi-peripheral debug strategy. ? emi external memory interface memory interface (emi) the emi includes ? multi-master memory interface (m3if) ? enhanced sdram controller (esdctl) ? nand flash controller (nfc) ? wireless external interface module (weim) ? 4.3.9.3/46 , 4.3.9.1/38 , 4.3.9.2/41 epit enhanced periodic interrupt timer timer peripheral the epit is a 32-bit ?set and forget ? timer which starts counting after the epit is enabled by software. it is capable of providing precise interrupts at regular intervals with minimal processor intervention. ? etm embedded trace macrocell debug/trace the etm (from arm, ltd.) su pports real-time instruction and data tracing by way of etm auxiliary i/o port. 4.3.10/54 fir fast infrared interface connectivity peripheral this fir is capable of establishing a 0.576 mbit/s, 1.152 mbit/s or 4 mbit/s half duplex link via a led and ir detector. it supports 0.576 mbit/s, 1.152 mbit/s medium infrared (mir) physical layer protocol and 4mbit/s fast infrared (fir) physical layer protocol defined by irda, rev. 1.4. 4.3.11/55
functional description and application information mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 7 fusebox fusebox rom the fusebox is a rom that is factory configured by freescale. 4.3.12/55 see also ta bl e 1 1 gpio general purpose i/o module pins the gpio provides several groups of 32-bit bidirectional, general purpose i/o. this peripheral provides dedicated general-purpose signals that can be configured as either inputs or outputs. ? gpt general purpose timer timer peripheral the gpt is a multipurpose module used to measure intervals or generate periodic output. ? gpu graphics processing unit multimedia peripheral the gpu provides hardware acceleration for 2d and 3d graphics algorithms. ? i 2 c inter ic communication connectivity peripheral the i 2 c provides serial interface for controlling the sensor interface and other external devices. data rates of up to 100 kbits/s are supported. 4.3.13/56 iim ic identification module id the iim provides an interface fo r reading device identification. ? ipu image processing unit multimedia peripheral the ipu processes video and graphics functions in the mcimx31 and interfaces to video, still image sensors, and displays. 4.3.14/57 , 4.3.15/59 kpp keypad port connectivity peripheral the kpp is used for keypad matrix scanning or as a general purpose i/o. this peripheral simplifies the software task of scanning a keypad matrix. ? mpeg-4 mpeg-4 video encoder multimedia peripherals the mpeg-4 encoder accelerates video compression, following the mpeg-4 standard ? mshc memory stick host controller connectivity peripheral the mshc is placed in between the aips and the customer memory stick to support data transfer from the mcimx31 to the customer memory stick. 4.3.16/84 padio pads i/o buffers and drivers the padio serves as the interface between the internal modules and the device's external connections. 4.3.1/22 pcmcia pcm connectivity peripheral the pcmcia host adapter provides the control logic for pcmcia socket interfaces. 4.3.17/86 pwm pulse-width modulator timer peripheral the pwm has a 16-bit counter and is optimized to generate sound from stored sample audio images. it can also generate tones. 4.3.18/88 rnga random number generator accelerator security the rnga module is a digital integrated circuit capable of generating 32-bit random numbers. it is designed to comply with fips-140 standards for randomness and non-determinism. ? rtc real time clock timer peripheral the rtc module provides a current stamp of seconds, minutes, hours, and days. alarm and timer functions are also available for programming. the rtc supports dates from the year 1980 to 2050. ? rtic run-time integrity checkers security the rtic ensures the integrity of the peripheral memory contents and assists with boot authentication. ? table 3. digital and analog modules (continued) block mnemonic block name functional grouping brief description section/ page
mcimx31/mcimx31l technical data, rev. 4.1 8 freescale semiconductor functional description and application information scc security controller module security the scc is a hardware component composed of two blocks?the secure ram module, and the secu rity monitor. the secure ram provides a way of securely storing sensitive information. ? sdhc secured digital host controller connectivity peripheral the sdhc controls the mmc (multim ediacard), sd (secure digital) memory, and i/o cards by sendi ng commands to cards and performing data accesses to and from the cards. 4.3.19/89 sdma smart direct memory access system control peripheral the sdma controller maximizes the system?s performance by relieving the arm core of the task of bulk data transfer from memory to memory or between memory and on-chip peripherals. ? sim subscriber identification module connectivity peripheral the sim interfaces to an external su bscriber identification card. it is an asynchronous serial interface adapted for smart card communication for e-commerce applications. 4.3.20/90 sjc secure jtag controller debug the sjc provides debug and test control with maximum security and provides a flexible architecture for future derivatives or future multi-cores architecture. 4.3.21/94 ssi synchronous serial interface multimedia peripheral the ssi is a full-duplex, serial port that allows the device to communicate with a variety of seri al devices, such as standard codecs, digital signal processors (dsps), microprocessors, peripherals, and popular industry audio codecs that implement the inter-ic sound bus standard (i2s) and intel ac97 standard. 4.3.22/96 uart universal asynchronous receiver/trans mitter connectivity peripheral the uart provides serial communication capability with external devices through an rs-232 cable or through use of external circuitry that converts infrared signals to electrical signals (for reception) or transforms electrical signals to signals that drive an infrared led (for transmission) to provide low speed irda compatibility. ? usb universal serial bus? 2 host controllers and 1 otg (on-the-go) connectivity peripherals ? usb host 1 is designed to support transceiverless connection to the on-board peripherals in low speed and full speed mode, and connection to the ulpi (utmi+ low-pin count) and legacy full speed transceivers. ? usb host 2 is designed to support transceiverless connection to the cellular modem baseband processor. ? the usb-otg controller offers hs/fs/ls capabilities in host mode and hs/fs in device mode. in host mode, the controller supports direct connection of a fs/ls device (without external hub). in device (bypass) mode, the otg port functions as gateway between the host 1 port and the otg transceiver. 4.3.23/104 wdog watchdog timer module timer peripheral the wdog module protects agains t system failures by providing a method for the system to recover from unexpected events or programming errors. ? table 3. digital and analog modules (continued) block mnemonic block name functional grouping brief description section/ page
signal descriptions mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 9 3 signal descriptions signal descriptions are in the reference manual. spec ial signal considerations are listed following this paragraph. the bga ba ll assignment is in section 5, ?package information and pinout .? special signal considerations: ? tamper detect (gpio1_6) tamper detect logic is used to is sue a security violation. this logic is activated if the tamper detect input is asserted. the tamper detect logic is disable d after reset. after enabling the l ogic, it is impos sible to disable it until the next reset. the gpr[16] bit fu nctions as the tamper detect enable bit. gpio1_6 functions similarly to other i/o with gpio capabilities regardless of the status of the tamper detect enable bit. (for example, the gpio1_6 can function as an input with gpio capabilities, such as sampling th rough psr or generating interrupts.) ? power ready (gpio1_5) the power ready input, gpio1_5, shoul d be connected to an external power management ic power ready output signal. if no t used, gpio1_5 must either be (a) externally pul led-up to nvcc1 or (b) a no connect, internally pulled-up by enabling the on-chip pull-up r esistor. gpio1_5 is a dedicated input and cannot be used as a general-purpose input/output. ? sjc_mod sjc_mod must be externally connected to gnd for normal operation. termination to gnd through an external pull-down resistor (such as 1 k ) is allowed, but the value should be much smaller than the on-chip 100 k pull-up. ? ce_control ce_control is a reserved input and must be externally tied to gnd through a 1 k resistor. ? ttm_pad ttm_pad is for freescale factory use only. contro l bits indicate pull-up/ down disabled. however, ttm_pad is actually connected to an on-chip pull- down device. users must either float this signal or tie it to gnd. ? m_request and m_grant these two signals are not utilized internally. the user should make no conne ction to these signals. ? clock source select (clkss) the clkss is the input that selects the default reference clock source provi ding input to the dpll. to select ckih, tie clkss to nvcc1. to select ckil, tie clks s to ground. after initialization, the reference clock source can be changed (ini tial setting is overwri tten) by programming the prcs bits in the ccmr.
mcimx31/mcimx31l technical data, rev. 4.1 10 freescale semiconductor electrical characteristics 4 electrical characteristics this section provides the device-level and module-le vel electrical character istics for the mcimx31. 4.1 chip-level conditions this section provides the device-level el ectrical characteris tics for the ic. see table 4 for a quick reference to the individual tables and sections. caution stresses beyond those listed under table 5 may cause permanent damage to the device. these are stress ratings only. functional operation of the device at these or any other conditi ons beyond those indicated under table 8, "operating ranges," on page 13 is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. table 4. mcimx31 chip-level conditions for these characteristi cs, ? topic appears ? table 5, ?absolute maximum ratings? on page 10 ta b l e 7 , ?thermal resistance data?19 19 mm package? on page 11 table 8, ?operating ranges? on page 13 ta b l e 9 , ?specific operating ranges for silicon revision 2.0? on page 14 table 10, ?interface frequency? on page 14 section 4.1.1, ?supply current specifications? on page 16 section 4.2, ?supply power-up/power-down requirements and restrictions? on page 19 table 5. absolute maximum ratings parameter symbol min max units supply voltage (core) qvcc max ?0.5 1.65 v supply voltage (i/o) nvcc max ?0.5 3.3 v input voltage range v imax ?0.5 nvcc +0.3 v storage temperature t storage ?40 125 o c esd damage immunity: v esd v human body model (hbm) ? 1500 machine model (mm) ? 200 charge device model (cdm) ? 500 offset voltage allowed in run mode between core supplies. v core_offset 1 1 the offset is the difference between all core vo ltage pair combinations of qvcc, qvcc1, and qvcc4. ?15mv
electrical characteristics mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 11 table 6 provides the thermal resistance data for the 14 14 mm, 0.5 mm pitch package. notes 1. junction temperature is a fu nction of die size, on-chip po wer dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. per jedec jesd51-2 with the single laye r board horizontal. board meets jesd51-9 specification. 3. per jedec jesd51-6 with the board horizontal. 4. thermal resistance between the die and the pr inted circuit board per jedec jesd51-8. board temperature is measured on the top surf ace of the board near the package. 5. thermal resistance between the die and the case top surface as m easured by the cold plate method (mil spec-883 method 1012.1). 6. thermal characterization parame ter indicating the temperature difference between package top and the junction temperature pe r jedec jesd51-2. when greek le tters are not available, the thermal characterization parame ter is written as psi-jt. table 7 provides the thermal resistance data for the 19 19 mm, 0.8 mm pitch package. table 6. thermal resistance data?14 14 mm package rating board symbol value unit notes junction to ambient (natural convection) single layer board (1s) r ja 56 c/w 1, 2, 3 junction to ambient (natural convection) four layer board (2s2p) r ja 30 c/w 1, 3 junction to ambient (@200 ft/min) single layer board (1s) r jma 46 c/w 1, 2, 3 junction to ambient (@200 ft/min) four layer board (2s2p) r jma 26 c/w 1, 3 junction to board ? r jb 17 c/w 1, 4 junction to case ? r jc 10 c/w 1, 5 junction to package top (natural convection) ? jt 2c/w1, 6 table 7. thermal resistance data?19 19 mm package rating board symbol value unit notes junction to ambient (natural convection) single layer board (1s) r ja 46 c/w 1, 2, 3 junction to ambient (natural convection) four layer board (2s2p) r ja 29 c/w 1, 2, 3 junction to ambient (@200 ft/min) single layer board (1s) r jma 38 c/w 1, 2, 3 junction to ambient (@200 ft/min) four layer board (2s2p) r jma 25 c/w 1, 2, 3 junction to board ? r jb 19 c/w 1, 3 junction to case (top) ? r jctop 10 c/w 1, 4 junction to package top (natural convection) ? jt 2c/w1, 5
mcimx31/mcimx31l technical data, rev. 4.1 12 freescale semiconductor electrical characteristics notes 1. junction temperature is a fu nction of die size, on-chip po wer dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. junction-to-ambient thermal resistance de termined per jedec jesd51-3 and jesd51-6. thermal test board m eets jedec specification for this package. 3. junction-to-board thermal resistance determ ined per jedec jesd51-8. thermal test board meets jedec specification for the specified package. 4. junction-to-case at the top of the package determined using mil-std 883 method 1012.1. the cold plate temperature is used for the case te mperature. reported value includes the thermal resistance of the interface layer. 5. thermal characterization parame ter indicating the temperature di fference between the package top and the junction temp erature per jedec jesd51-2. when gree k letters are not available, the thermal characterization parame ter is written as psi-jt.
electrical characteristics mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 13 table 8 provides the operating ranges. note the term nvcc in this section refers to the associated supply rail of an input or output. the association is sh own in the signal multiplexing chapter of the reference manual. caution nvcc6 and nvcc9 must be at the sam e voltage potential. these supplies are connected together on-chip to optimize esd da mage immunity. table 8. operating ranges symbol parameter min max units qvcc, qvcc1, qvcc4 core operating voltage 1,2,3 1 measured at package balls, including peripherals, arm, and l2 cache supplies (qvcc, qvcc1, qvcc4, respectively). 2 the core voltage must be higher than 1.38v to avoid corrupt ed data during transfers from the usb hs. please refer to errata file engcm02610 id. 3 if the core voltage is supplied by the mc13738, it will be 1. 6 0.05 v during the power-up sequ ence. this is allowed. after power-up the voltage should be reduced to avoid operation in overdrive mode. v silicon rev 1.15, 1.2, and 2.0 0 f arm 400 mhz, non-overdrive 0 f arm 400 mhz, overdrive 4 0 f arm 532 mhz, overdrive 4 4 supply voltage is considered ?overdrive? for voltages above 1.47 v. operation time in overdrive?whether switching or not?must be limited to a cumulative duration of 1.25 years (10, 950 hours) or less to sustain the maximum operating voltage without significant device degr adation?for example, 25% (average 6 hours out of 24 yours per day) duty cycle for 5-year rated equipment. to tolerate the maxi mum operating overdrive voltage for 10 years, the device must have a duty cycle of 12.5% or less in overdrive (for example 3 out of 24 hours per day). belo w 1.47v, duty cycle restrictions may apply for equipment rated above 5 years. 1.22 >1.47 1.55 1.47 1.65 1.65 state retention voltage 5 5 the sr voltage is applied to qvcc, qvcc1, and qvcc4 after the device is placed in sr mode. the real-time clock (rtc) is operational in state retention (sr) mode . 0.95 ? nvcc1, nvcc3?10 i/o supply voltage, except ddr 6 non-overdrive overdrive 7 6 overshoot and undershoot conditions (transitions above nvcc and below gnd) on i/o must be held below 0.6 v, and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. overshoot/undershoot must be controlled through printed circuit board layout, transmission lin e impedance matching, signal li ne termination, or other methods. non-compliance to this specification may affect de vice reliability or cause permanent damage to the device. 1.75 >3.1 3.1 3.3 v nvcc2, nvcc21, nvcc22 i/o supply voltage, ddr only 1.75 1.95 v fvcc, mvcc, svcc, uvcc pll (phase-locked loop) and fpm (freque ncy pre-multiplier) supply voltage 8 non-overdrive overdrive 4 1.3 >1.47 1.47 1.6 v ioqvdd on-device level shifter supply voltage 1.6 1.9 v fuse_vdd fusebox read supply voltage 9, 10 1.65 1.95 v fusebox write (program) supply voltage 11 3.0 3.3 v t a operating ambient temperature range 12 070 o c
mcimx31/mcimx31l technical data, rev. 4.1 14 freescale semiconductor electrical characteristics table 10 provides information for interface frequency limits . for more details about clocks characteristics, see section 4.3.8, ?dpll electrical specifications ,? and section 4.3.3, ?clock amplifier module (camp) electrical characteristics .? table 11 shows the fusebox supply current parameters. 7 supply voltage is considered ?overdrive? for voltages above 3.1 v. operation time in overdrive?whether switching or not?must be limited to a cumulative duration of 1 year (8,760 hours) or less to sustain the maximum operating voltage without significant device degrada tion?for example, 20% (average 4.8 hours out of 24 hours per day) duty cycle for 5-year rated equipment. operation at 3.3 v that exceeds a cumulative 3, 504 hours may cause non-operation whenever supply voltage is reduced to 1.8 v; degradation may render the device too slow or inoperable. below 3.1 v, duty cycle restrictions may apply for equipment rated above 5 years. 8 for normal operating conditions, plls? and core supplies must maintain the following relation: pll core ? 100 mv. in other words, for a 1.6 v core supply, pll supplies must be set to 1.5 v or higher. this restriction is no longer necessary on mask set m91e. pll supplies may be set independently of core supply. pll voltage must not be altered after power up, otherwise the pll will be unstable and lose lock. to minimize inducing no ise on the pll supply line, source the voltage from a low-noise, dedicated supply. pll parameters in table 31, "dpll specifications," on page 37 , are guaranteed over the entire specified voltage range. 9 fusebox read supply voltage applies to silicon revisions 1.2 and previous. 10 in read mode, fuse_vdd can be floated or groun ded for mask set m91e (silicon revision 2.0). 11 fuses might be inadvertently blown if written to while the voltage is below this minimum. 12 the temperature range given is for the consumer version. please refer to ta b l e 1 for extended temperature range offerings and the associated part numbers. table 9. specific operating ranges for silicon revision 2.0 symbol parameter min max units fuse_vdd fusebox read supply voltage 1 1 in read mode, fuse_vdd should be floated or grounded. ?? v fusebox write (program) supply voltage 2 2 fuses might be inadvertently blown if written to while the voltage is below the minimum. 3.0 3.3 v table 10. interface frequency id parameter symbol min typ max units 1 jtag tck frequency f jtag dc 5 10 mhz 2 ckil frequency 1 1 ckil must be driven by an external clock source to ensure pr oper start-up and operation of the device. ckil is needed to clock the internal reset synchronizer, the watchdog, and the real-time clock. f ckil 32 32.768 38.4 khz 3 ckih frequency 2 2 dptc functionality, specifically the voltag e/frequency relation table, is dependent on ck ih frequency. at the time of publicati on, standard tables used by freescale oss provided for a ckih fr equency of 26 mhz only. any deviation from this frequency requires an update to the os. for more details, refer to the particular os user's guide documentation. f ckih 15 26 75 mhz
electrical characteristics mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 15 table 11. fusebox supply current parameters ref. num description symbol minimum typical maximum units 1 efuse program current. 1 current to program one efuse bit: efuse_pgm = 3.0 v 1 the current i program is during program time (t program ). i program ?3560ma 2 efuse read current 2 current to read an 8-bit efuse word vdd_fusebox = 1.875 v 2 the current i read is present for approximately 50 ns of the read access to the 8-bit word, and only applies to silicon rev. 1.2 and previous. i read ?5 8ma
mcimx31/mcimx31l technical data, rev. 4.1 16 freescale semiconductor electrical characteristics 4.1.1 supply current specifications table 12 shows the core current consumption for 0 c to 70 c for silicon revision 1.2 and previous for the mcimx31. table 12. current consumption for 0 c to 70 c 1, 2 for silicon revision 1.2 and previous 1 typical column: ta = 25 c 2 maximum column: ta = 70 c mode conditions qvcc (peripheral) qvcc1 (arm) qvcc4 (l2) fvcc + mvcc + svcc + uvcc (pll) unit typ max typ max typ max typ max state retention ? qvcc and qvcc1 = 0.95 v ? l2 caches are power gated (qvcc4 = 0 v) ? all plls are off, vcc = 1.4 v ? arm is in well bias ?fpm is off ? 32 khz input is on ? ckih input is off ? camp is off ? tck input is off ? all modules are off ? no external resistive loads ? rnga oscillator is off 0.80 ? 0.50 ? ? ? 0.04 ? ma wait ? qvcc,qvcc1, and qvcc4 = 1.22 v ? arm is in wait for interrupt mode ? max is active ? l2 cache is stopped but powered ? mcu pll is on (532 mhz), vcc = 1.4 v ? usb pll and spll are off, vcc = 1.4 v ?fpm is on ? ckih input is on ? camp is on ? 32 khz input is on ? all clocks are gated off ? all modules are off (by programming cgr[2:0] registers) ? rnga oscillator is off ? no external resistive loads 6.00 ? 3.00 ? 0.04 ? 3.50 ? ma
electrical characteristics mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 17 table 13 shows the core curre nt consumption for ?40 c to 85 c for silicon revision 2.0 for the mcimx31. table 13. current consumption for ?40 c to 85 c 1, 2 for silicon revision 2.0 1 typical column: ta = 25 c 2 maximum column: ta = 85 c mode conditions qvcc (peripheral) qvcc1 (arm) qvcc4 (l2) fvcc + mvcc + svcc + uvcc (pll) unit typ max typ max typ max typ max deep sleep ? qvcc = 0.95 v ? arm and l2 caches are power gated (qvcc1 = qvcc4 = 0 v) ? all plls are off, vcc = 1.4 v ? arm is in well bias ?fpm is off ? 32 khz input is on ? ckih input is off ? camp is off ? tck input is off ? all modules are off ? no external resistive loads ? rnga oscillator is off 0.16 5.50 ? ? ? ? 0.02 0.10 ma state retention ? qvcc and qvcc1 = 0.95 v ? l2 caches are power gated (qvcc4 = 0 v) ? all plls are off, vcc = 1.4 v ? arm is in well bias ?fpm is off ? 32 khz input is on ? ckih input is off ? camp is off ? tck input is off ? all modules are off ? no external resistive loads ? rnga oscillator is off 0.16 5.50 0.07 2.20 ? ? 0.02 0.10 ma wait ? qvcc,qvcc1, and qvcc4 = 1.22 v ? arm is in wait for interrupt mode ? max is active ? l2 cache is stopped but powered ? mcu pll is on (532 mhz), vcc = 1.4 v ? usb pll and spll are off, vcc = 1.4 v ?fpm is on ? ckih input is on ? camp is on ? 32 khz input is on ? all clocks are gated off ? all modules are off (by programming cgr[2:0] registers) ? rnga oscillator is off ? no external resistive loads 6.00 15.00 2.20 25.00 0. 03 0.29 3.60 4.40 ma
mcimx31/mcimx31l technical data, rev. 4.1 18 freescale semiconductor electrical characteristics table 14 shows the core current consumption for 0 c to 70 c for silicon revision 2.0 for the mcimx31. table 14. current consumption for 0 c to 70 c 1, 2 for silicon revision 2.0 1 typical column: ta = 25 c 2 maximum column: ta = 70 c mode conditions qvcc (peripheral) qvcc1 (arm) qvcc4 (l2) fvcc, +mvcc, +svcc, +uvcc (pll) unit typ max typ max typ max typ max deep sleep ?qvcc = 0.95v ? arm and l2 caches are power gated (qvcc1 2= qvcc4 = 0 v) ? all plls are off, vcc = 1.4 v ? arm is in well bias ? fpm is off ? 32 khz input is on ? ckih input is off ? camp is off ? tck input is off ? all modules are off ? no external resistive loads ? rnga oscillator is off 0.16 2.50 ? ? ? ? 0.02 0.10 ma state retention ? qvcc and qvcc1 = 0.95 v ? l2 caches are power gated (qvcc4 = 0 v) ? all plls are off, vcc = 1.4 v ? arm is in well bias ? fpm is off ? 32 khz input is on ? ckih input is off ? camp is off ? tck input is off ? all modules are off ? no external resistive loads ? rnga oscillator is off 0.16 2.50 0.07 1.60 ? ? 0.02 0.10 ma wait ? qvcc,qvcc1, and qvcc4 = 1.22 v ? arm is in wait for interrupt mode ? max is active ? l2 cache is stopped but powered ? mcu pll is on (532 mhz), vcc = 1.4 v ? usb pll and spll are off, vcc = 1.4 v ? fpm is on ? ckih input is on ? camp is on ? 32 khz input is on ? all clocks are gated off ? all modules are off (by programming cgr[2:0] registers) ? rnga oscillator is off ? no external resistive loads 6.00 13.00 2.20 16.00 0.03 0.17 3.60 4.40 ma
electrical characteristics mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 19 4.2 supply power-up/power-down requirements and restrictions any mcimx31 board design must comply with the power-up and power-down sequence guidelines as described in this section to guarantee reliable opera tion of the device. any devi ation from these sequences may result in any or all of the following situations: ? cause excessive curr ent during power up phase ? prevent the device from booting ? cause irreversible damage to the mcimx31 (worst-case scenario) 4.2.1 powering up the power on reset (por ) pin must be kept asser ted (low) throughout the powe r up sequence. power up logic must guarantee that all power sources reach their target values prior to the rele ase (de-assertion) of por . figure 2 shows the power-up sequence for si licon revisions 1.2 and previous. figure 3 and figure 4 show the power-up sequence for silicon revision 2.0. note stages need to be performed in the order shown; however, within each stage, supplies can be powered up in any order. for example, supplies ioqvdd, nvcc1, and nvcc3 through nvcc10 do not need to be powered up in the order shown. caution nvcc6 and nvcc9 must be at the sam e voltage potential. these supplies are connected together on-chip to optimize esd da mage immunity.
mcimx31/mcimx31l technical data, rev. 4.1 20 freescale semiconductor electrical characteristics figure 2. power-up sequence for silicon revisions 1.2 and previous 4.2.1.1 power-up sequence for silicon revision 2 silicon revision 2.0 offers two options for power-up sequencing. option 1 is backwards compatible with silicon revision 1.2 and earlier versions of the ic. it should be noted that using option 1 on silicon rev. 2.0 introduces a slight increase in current drain on io qvdd when ioqvdd is raised before nvcc21. the expected resulting increase is in the range of 3 ma to 5 ma, which does not pose a risk to the ic. option 2 is an alternative power-up sequence that allows the powering up of nvcc2, nvcc21, nvcc22 with ioqvdd, nvcc1, and nvcc3 -10 without producing a curren t drain increase on ioqvdd. these two power-up options on the 2.0 silicon allow the user to select the optimum power-up sequence for their application. release por qvcc, qvcc1, qvcc4 ioqvdd, nvcc1, nvcc3?10 fvcc, mvcc, svcc, uvcc nvcc2, nvcc21, nvcc22 fuse_vdd hold por asserted 1 1 1, 2 1 1 1, 3 notes: 1 the board design must guarantee that s upplies reach 90% level before transition to the next state, using power management ic or other means. 2 the nvcc1 supply must not precede ioqvdd by more than 0.2 v until ioqvdd has reached 1.5 v. if ioqvdd is powered up first, there are no restrictions. 3 it is allowable for fvcc, mvcc, svcc, and uvcc to be up after fuse_vdd.
electrical characteristics mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 21 figure 3. option 1 power-up sequence (silicon revision 2.0) figure 4. option 2 power-up sequence (silicon revision 2.0) release por qvcc, qvcc1, qvcc4 ioqvdd, nvcc1, nvcc3?10 nvcc2, nvcc21, nvcc22 hold por asserted 1 1, 2 1, 3, 5 notes: 1 the board design must guarantee that supplies reach 90% level before transition to the next state, using power management ic or other means. 2 the nvcc1 supply must not precede ioqvdd by more than 0.2 v until ioqvdd has reached 1.5 v. if ioqvdd is powered up first, there are no restrictions. 3 the parallel paths in the flow indicate that supply group nvcc2, nvcc21, and nvcc22, and supply group fvcc, mvcc, svcc, and uvcc ramp-ups are independent. note that this power-up sequence is backward compatible to silicon revs. 1.15 and 1.2, because nvcc2x ramp-up proc eeding pll supplies is allowed. 4 unlike the power-up sequence for silicon revision 1.2, fuse_vdd should not be driven on power-up for silicon revision 2.0. this supply is dedicated for fuse burning (programming), and should not be driven upon boot-up. 5 raising ioqvdd before nvcc21 produces a slight increase in current drain on ioqvdd of approximately 3?5 ma. the current increase will not damage the ic. refer to errata id tlsbo91750 for details. fvcc, mvcc, svcc, uvcc 1,3 4 release por qvcc, qvcc1, qvcc4 ioqvdd, nvcc1, nvcc3?10, nvcc2, nvcc21, nvcc22 hold por asserted 1 1, 2,3 notes: 1 the board design must guar antee that supplies reach 90% level before transition to the next state, using power management ic or other means. 2 the nvcc1 supply must not precede ioqvdd by more than 0.2 v until ioqvdd has reached 1.5 v. if ioqvdd is powered up first, there are no restrictions. 3 raising nvcc2, nvcc21, and nvcc22 at the same time as ioqvdd does not produc e the slight increase in current drain on ioqvdd (as described in figure 3 , note 5). 4 unlike the power-up sequence for silicon revision 1.2, fuse_vdd should not be driv en on power-up for silicon revision 2.0. this supply is dedicated for fuse burning (programming), and should not be driven upon boot-up. fvcc, mvcc, svcc, uvcc 1 4
mcimx31/mcimx31l technical data, rev. 4.1 22 freescale semiconductor electrical characteristics 4.2.2 powering down the power-down sequence prior to silicon re vision 2.0 should be completed as follows: 1. lower the fuse_vdd supply (when in write mode). 2. lower the remaining supplies. for silicon revisions beginning with revision 2.0 there is no special requirements for power down sequence. 4.3 module-level electrical specifications this section contains the mcimx31 electrical info rmation including timing spec ifications, arranged in alphabetical order by module name. 4.3.1 i/o pad (padio) electrical specifications this section specifies the ac/dc ch aracterization of functional i/o of the mcimx31. there are two main types of i/o: regular and ddr. in this document, the ?regular? type is referred to as gpio. 4.3.1.1 dc electrical characteristics the mcimx31 i/o parameters appear in table 15 for gpio. see table 8 for temperature and supply voltage ranges. note the term nvcc in this section refers to the associated supply rail of an input or output. the association is sh own in the signal multiplexing chapter of the reference manual. nvcc for table 15 refers to nvcc1 and nvcc3?10; qvcc refers to qvcc, qvcc 1, and qvcc4. table 15. gpio dc electrical parameters parameter symbol test cond itions min typ max units high-level output voltage v oh i oh = ?1 ma nvcc ?0.15 ? ? v i oh = specified drive 0.8*nvcc ? ? v low-level output voltage v ol i ol = 1 ma ? ? 0.15 v i ol = specified drive ? ? 0.2*nvcc v high-level output current, slow slew rate i oh_s v oh =0.8*nvcc std drive high drive max drive ?2 ?4 ?8 ??ma high-level output current, fast slew rate i oh_f v oh =0.8*nvcc std drive high drive max drive ?4 ?6 ?8 ??ma
electrical characteristics mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 23 the mcimx31 i/o parameters appear in table 16 for ddr (double data rate). see table 8, "operating ranges," on page 13 for temperature and supply voltage ranges. note nvcc for table 16 refers to nvcc2, nvcc21, and nvcc22. low-level output current, slow slew rate i ol_s v ol =0.2*nvcc std drive high drive max drive 2 4 8 ??ma low-level output current, fast slew rate i ol_f v ol =0.2*nvcc std drive high drive max drive 4 6 8 ??ma high-level dc input voltage v ih ? 0.7*nvcc ? nvcc v low-level dc input voltage v il ?0?0.3*qvccv input hysteresis v hys hysteresis enabled 0.25 ? ? v schmitt trigger vt+ v t + hysteresis enabled 0.5*qvcc ? ? v schmitt trigger vt? v t ? hysteresis enabled ? ? 0.5*qvcc v pull-up resistor (100 k pu) r pu ? ? 100 ? k pull-down resistor (100 k pd) r pd ? ? 100 ? input current (no pu/pd) i in v i = nvcc or gnd ? ? 1 a input current (100 k pu) i in v i = 0 v i = nvcc ??25 0.1 a a input current (100 k pd) i in v i = 0 v i = nvcc ? ? 0.25 28 a a tri-state leakage current i oz v i = nvcc or gnd i/o = high z ?? 2 a table 16. ddr (double data rate) i/o dc electrical parameters parameter symbol test conditions min typ max units high-level output voltage v oh i oh = ?1 ma nvcc ?0.12 ? ? v i oh = specified drive 0.8*nvcc ? ? v low-level output voltage v ol i ol = 1 ma ? ? 0.08 v i ol = specified drive ? ? 0.2*nvcc v high-level output current i oh v oh =0.8*nvcc std drive high drive max drive ddr drive 1 ?3.6 ?7.2 ?10.8 ?14.4 ??ma table 15. gpio dc electrical parameters (continued) parameter symbol test cond itions min typ max units
mcimx31/mcimx31l technical data, rev. 4.1 24 freescale semiconductor electrical characteristics 4.3.2 ac electrical characteristics figure 5 depicts the load circuit for outputs. figure 6 depicts the output transi tion time waveform. the range of operating c onditions appears in table 17 for slow general i/o, table 18 for fast general i/o, and table 19 for ddr i/o (unless otherwise noted). figure 5. load circuit for output figure 6. output transition time waveform low-level output current i ol v ol =0.2*nvcc std drive high drive max drive ddr drive 1 3.6 7.2 10.8 14.4 ??ma high-level dc input voltage v ih ? 0.7*nvcc nvcc nvcc+0.3 v low-level dc input voltage v il ? ?0.3 0 0.3*nvcc v tri-state leakage current i oz v i = nvcc or gnd i/o = high z ?? 2 a 1 use of ddr drive can result in excessive overshoot and ringing. table 17. ac electrical characteristics of slow 1 general i/o 1 fast/slow characteristic is selected per gpio (where available) by ?slew rate? control. see reference manual. id parameter symbol test condition min typ max units pa1 output transition times (max drive) tpr 25 pf 50 pf 0.92 1.5 1.95 2.98 3.17 4.75 ns output transition times (high drive) tpr 25 pf 50 pf 1.52 2.75 ?4.81 8.42 ns output transition times (std drive) tpr 25 pf 50 pf 2.79 5.39 ?8.56 16.43 ns table 16. ddr (double data rate) i/o dc electrical parameters (continued) parameter symbol test conditions min typ max units te s t po i n t from output under test cl cl includes package, probe and fixture capacitance 0v nvcc 20% 80% 80% 20% pa 1 pa 1 output (at i/o)
electrical characteristics mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 25 4.3.3 clock amplifier module (cam p) electrical characteristics this section outlines the clock amplifier module (camp) specific elect rical characteristics. table 20 shows clock amplifier electrical characteristics. table 18. ac electrical characteristics of fast 1 general i/o 2 1 fast/slow characteristic is selected per gpio (where available) by ?slew rate? control. see reference manual. 2 use of gpio in fast mode with the associated nvcc > 1.95 v can result in excessive overshoot and ringing. id parameter symbol test condition min typ max units pa1 output transition times (max drive) tpr 25 pf 50 pf 0.68 1.34 1.33 2.6 2.07 4.06 ns output transition times (high drive) tpr 25 pf 50 pf .91 1.79 1.77 3.47 2.74 5.41 ns output transition times (std drive) tpr 25 pf 50 pf 1.36 2.68 2.64 5.19 4.12 8.11 ns table 19. ac electrical characteristics of ddr i/o id parameter symbol test condition min typ max units pa1 output transition times (ddr drive) 1 1 use of ddr drive can result in excessive overshoot and ringing. tpr 25 pf 50 pf 0.51 0.97 0.82 1.58 1.28 2.46 ns output transition times (max drive) tpr 25 pf 50 pf 0.67 1.29 1.08 2.1 1.69 3.27 ns output transition times (high drive) tpr 25 pf 50 pf .99 1.93 1.61 3.13 2.51 4.89 ns output transition times (std drive) tpr 25 pf 50 pf 1.96 3.82 3.19 6.24 4.99 9.73 ns table 20. clock amplifier electrical characteristics for ckih input parameter min typ max units input frequency 15 ? 75 mhz vil (for square wave input) 0 ? 0.3 v vih (for square wave input) (vdd 1 ? 0.25) 1 vdd is the supply voltage of camp. see reference manual. ?3v sinusoidal input amplitude 0.4 2 2 this value of the sinusoidal input will be measured through characterization. ?vddvp-p duty cycle 45 50 55 %
mcimx31/mcimx31l technical data, rev. 4.1 26 freescale semiconductor electrical characteristics 4.3.4 1-wire electrical specifications figure 7 depicts the rpp timing, and table 21 lists the rpp timing parameters. figure 7. reset and presence pulses (rpp) timing diagram figure 8 depicts write 0 sequence timing, and table 22 lists the timing parameters. figure 8. write 0 sequence timing diagram figure 9 depicts write 1 sequence timing, figure 10 depicts the read sequence timing, and table 23 lists the timing parameters. table 21. rpp sequence delay comparisons timing parameters id parameters symbol min typ max units ow1 reset time low t rstl 480 511 ? s ow2 presence detect high t pdh 15 ? 60 s ow3 presence detect low t pdl 60 ? 240 s ow4 reset time high t rsth 480 512 ? s table 22. wr0 sequence timing parameters id parameter symbol min typ max units ow5 write 0 low time t wr0_low 60 100 120 s ow6 transmission time slot t slot ow5 117 120 s 1-wire bus ds2502 tx ?presence pulse? (batt_line) owire tx ?reset pulse? ow1 ow2 ow3 ow4 ow5 ow6 1-wire bus (batt_line)
electrical characteristics mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 27 figure 9. write 1 sequence timing diagram figure 10. read sequence timing diagram 4.3.5 ata electrical specifications (ata bus, bus buffers) this section discusses ata parameters. for a deta iled description, refer to the ata specification. the user needs to use level shifters for 3.3 volt or 5.0 volt compatibi lity on the ata interface. the use of bus buffers introduces delay on the bus and introduces skew between si gnal lines. these factors make it difficult to operate the bus at the highest speed (udma-5) when bus buffers are used. if fast udma mode operation is needed, this ma y not be compatible with bus buffers. another area of attention is the slew rate limit imposed by th e ata specification on the ata bus. according to this limit, any signal driven on the bus should have a slew rate between 0.4 and 1.2 v/ns with a 40 pf load. not many vendors of bus buffers specify slew rate of the outgoing signals. when bus buffers are used, the ata_data bus buffer is special. this is a bidirectional bus buffer, so a direction control signal is needed. this direction control signal is at a_buffer_en. when its high, the bus should drive from host to device. when its low, the bus should drive from device to host. steering of the signal is such that contention on the host and device tri-state busse s is always avoided. table 23. wr1/rd timing parameters id parameter symbol min typ max units ow7 write 1 / read low time t low1 1 5 15 s ow8 transmission time slot t slot 60 117 120 s ow9 release time t release 15 ? 45 s ow7 ow8 1-wire bus (batt_line) ow7 ow8 ow9 1-wire bus (batt_line)
mcimx31/mcimx31l technical data, rev. 4.1 28 freescale semiconductor electrical characteristics 4.3.5.1 timing parameters in the timing equations, some timi ng parameters are used. these para meters depend on the implementation of the ata interface on silicon, the bus buff er used, the cable delay and cable skew. table 24 shows ata timing parameters. table 24. ata timing parameters name description value/ contributing factor 1 1 values provided where applicable. t bus clock period (ipg_clk_ata) peripheral clock frequency ti_ds set-up time ata_data to ata_iordy edge (udma-in only) udma0 udma1 udma2, udma3 udma4 udma5 15 ns 10 ns 7 ns 5 ns 4 ns ti_dh hold time ata_iordy edge to ata_data (udma-in only) udma0, udma1, udma2, udma3, udma4 udma5 5.0 ns 4.6 ns tco propagation delay bus clock l-to-h to ata_cs0, ata_cs1, ata_da2, at a_da1, ata_da0, ata_dior, at a_diow, ata_dmack, ata_data, ata_buffer_en 12.0 ns tsu set-up time ata_data to bus clock l-to-h 8.5 ns tsui set-up time ata_iordy to bus clock h-to-l 8.5 ns thi hold time ata_iordy to bus clock h to l 2.5 ns tskew1 max difference in propagation delay bus clock l-to-h to any of following signals ata_cs0, ata_cs1, ata_da2, at a_da1, ata_da0, ata_dior, at a_diow, ata_dmack, ata_data (write), ata_buffer_en 7ns tskew2 max difference in buffer propagation delay for any of following signals ata_cs0, ata_cs1, ata_da2, at a_da1, ata_da0, ata_dior, at a_diow, ata_dmack, ata_data (write), ata_buffer_en transceiver tskew3 max difference in buffer propagation delay for any of following signals ata_iordy, ata_data (read) transceiver tbuf max buffer propagation delay transceiver tcable1 cable propagation delay for ata_data cable tcable2 cable propagation delay for control signal s ata_dior, ata_diow, ata_iordy, ata_dmack cable tskew4 max difference in cable propagation delay between ata_iordy and ata_data (read) cable tskew5 max difference in cable propagation delay between (ata_dior, ata_diow, ata_dmack) and ata_cs0, ata_cs1, ata_da2, ata _da1, ata_da0, ata_data(write) cable tskew6 max difference in cable propagation delay without accounting for ground bounce cable
electrical characteristics mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 29 4.3.5.2 pio mode timing figure 11 shows timing for pio read, and table 25 lists the timing parameters for pio read. figure 11. pio read timing diagram figure 12 shows timing for pio write, and table 26 lists the timing parameters for pio write. table 25. pio read timing parameters ata parameter parameter from figure 11 value controlling variable t1 t1 t1 (min) = time_1 * t ? (tskew1 + tskew2 + tskew5) time_1 t2 t2r t2 min) = time_2r * t ? (t skew1 + tskew2 + tskew5) time_2r t9 t9 t9 (min) = time_9 * t ? (tskew1 + tskew2 + tskew6) time_3 t5 t5 t5 (min) = tco + tsu + tbuf + tbuf + tcable1 + tcable2 if not met, increase time_2 t6 t6 0 ? ta ta ta (min) = (1.5 + time_ax) * t ? (tco + tsui + tcable2 + tcable2 + 2*tbuf) time_ax trd trd1 trd1 (max) = (?trd) + (tskew3 + tskew4) trd1 (min) = (time_pio_rdx ? 0.5)*t ? (tsu + thi) (time_pio_rdx ? 0.5) * t > tsu + thi + tskew3 + tskew4 time_pio_rdx t0 ? t0 (min) = (time_1 + time_2 + time_9) * t time_1, time_2r, time_9
mcimx31/mcimx31l technical data, rev. 4.1 30 freescale semiconductor electrical characteristics figure 12. multiword dma (mdma) timing figure 13 shows timing for mdma read, figure 14 shows timing for mdma write, and table 27 lists the timing parameters for mdma read and write. table 26. pio write timing parameters ata parameter parameter from figure 12 value controlling variable t1 t1 t1 (min) = time_1 * t ? (tskew1 + tskew2 + tskew5) time_1 t2 t2w t2 (min) = time_2w * t ? (tskew1 + tskew2 + tskew5) time_2w t9 t9 t9 (min) = time_9 * t ? (tskew1 + tskew2 + tskew6) time_9 t3 ? t3 (min) = (time_2w ? time_on)* t ? (tskew1 + tskew2 +tskew5) if not met, increase time_2w t4 t4 t4 (min) = time_4 * t ? tskew1 time_4 ta ta ta = (1.5 + time_ax) * t ? (tco + tsui + tcable2 + tcable2 + 2*tbuf) time_ax t0 ? t0(min) = (time_1 + time_2 + time_9) * t time_1, time_2r, time_9 ? ? avoid bus contention when switching buffer on by making ton long enough. ? ? ? avoid bus contention when switching buffer off by making toff long enough. ?
electrical characteristics mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 31 figure 13. mdma read timing diagram figure 14. mdma write timing diagram table 27. mdma read and write timing parameters ata parameter parameter from figure 13 , figure 14 value controlling variable tm, ti tm tm (min) = ti (min) = time_m * t ? (tskew1 + tskew2 + tskew5) time_m td td, td1 td1.(min) = td (min) = time_d * t ? (tskew1 + tskew2 + tskew6) time_d tk tk tk.(min) = time_k * t ? (tskew1 + tskew2 + tskew6) time_k t0 ? t0 (min) = (time_d + time_k) * t time_d, time_k tg(read) tgr tgr (min-read) = tco + tsu + tbuf + tbuf + tcable1 + tcable2 tgr.(min-drive) = td ? te(drive) time_d tf(read) tfr tfr (min-drive) = 0 ? tg(write) ? tg (min-write) = time_d * t ? (tskew1 + tskew2 + tskew5) time_d tf(write) ? tf (min-write) = time_k * t ? (tskew1 + tskew2 + tskew6) time_k tl ? tl (max) = (time_d + time_k?2)*t ? (tsu + tco + 2*tbuf + 2*tcable2) time_d, time_k tn, tj tkjn tn= tj= tkjn = (max(time_k,. time_j n) * t ? (tskew1 + tskew2 + tskew6) time_jn ?ton toff ton = time_on * t ? tskew1 toff = time_off * t ? tskew1 ?
mcimx31/mcimx31l technical data, rev. 4.1 32 freescale semiconductor electrical characteristics 4.3.5.3 udma in timing figure 15 shows timing when the udma in transfer starts, figure 16 shows timing when the udma in host terminates transfer, figure 17 shows timing when the udma in device terminates transfer, and table 28 lists the timing parameters for udma in burst. figure 15. udma in transfer starts timing diagram figure 16. udma in host terminates transfer timing diagram
electrical characteristics mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 33 figure 17. udma in device terminates transfer timing diagram table 28. udma in burst timing parameters ata parameter parameter from figure 15 , figure 16 , figure 17 description controlling variable tack tack tack (min) = (time_ack * t) ? (tskew1 + tskew2) time_ack tenv tenv tenv (min) = (time_env * t) ? (tskew1 + tskew2) tenv (max) = (time_env * t) + (tskew1 + tskew2) time_env tds tds1 tds ? (tskew3) ? ti_ds > 0 tskew3, ti_ds, ti_dh should be low enough tdh tdh1 tdh ? (tskew3) ? ti_dh > 0 tcyc tc1 (tcyc ? tskew) > t t big enough trp trp trp (min) = time_rp * t ? (tskew1 + tskew2 + tskew6) time_rp ?tx1 1 1 there is a special timing requirement in the ata host that require s the internal diow to go only high 3 clocks after the last active edge on the dstrobe signal. the equation given on this line tries to capture this constraint. 2. make ton and toff big enough to avoid bus contention (time_rp * t) ? (tco + tsu + 3t + 2 *tbuf + 2*tcable2) > trfs (drive) time_rp tmli tmli1 tmli1 (min) = (time_mlix + 0.4) * t time_mlix tzah tzah tzah (min) = (time_zah + 0.4) * t time_zah tdzfs tdzfs tdzfs = (time_dzfs * t) ? (tskew1 + tskew2) time_dzfs tcvh tcvh tcvh = (time_cvh *t) ? (tskew1 + tskew2) time_cvh ?ton toff ton = time_on * t ? tskew1 toff = time_off * t ? tskew1 ?
mcimx31/mcimx31l technical data, rev. 4.1 34 freescale semiconductor electrical characteristics 4.3.5.4 udma out timing figure 18 shows timing when the udma out transfer starts, figure 19 shows timing when the udma out host terminates transfer, figure 20 shows timing when the udma out device terminates transfer, and table 29 lists the timing parameters for udma out burst. figure 18. udma out transfer starts timing diagram figure 19. udma out host terminates transfer timing diagram
electrical characteristics mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 35 figure 20. udma out device terminates transfer timing diagram table 29. udma out burst timing parameters ata parameter parameter from figure 18 , figure 19 , figure 20 value controlling variable tack tack tack (min) = (time_ack * t) ? (tskew1 + tskew2) time_ack tenv tenv tenv (min) = (time_env * t) ? (tskew1 + tskew2) tenv (max) = (time_env * t) + (tskew1 + tskew2) time_env tdvs tdvs tdvs = (time_dvs * t) ? (tskew1 + tskew2) time_dvs tdvh tdvh tdvs = (time_dvh * t) ? (tskew1 + tskew2) time_dvh tcyc tcyc tcyc = time_cyc * t ? (tskew1 + tskew2) time_cyc t2cyc ? t2cyc = time_cyc * 2 * t time_cyc trfs1 trfs trfs = 1.6 * t + tsui + tco + tbuf + tbuf ? ? tdzfs tdzfs = time_dzfs * t ? (tskew1) time_dzfs tss tss tss = time_ss * t ? (tskew1 + tskew2) time_ss tmli tdzfs_mli tdzfs_mli =max (time_dzfs, time_mli) * t ? (tskew1 + tskew2) ? tli tli1 tli1 > 0 ? tli tli2 tli2 > 0 ? tli tli3 tli3 > 0 ? tcvh tcvh tcvh = (time_cvh *t) ? (tskew1 + tskew2) time_cvh ?ton toff ton = time_on * t ? tskew1 toff = time_off * t ? tskew1 ?
mcimx31/mcimx31l technical data, rev. 4.1 36 freescale semiconductor electrical characteristics 4.3.6 audmux electrical specifications the audmux provides a programmable interconnect logic for voice, audio and data routing between internal serial interfaces (ssi) and external serial interfaces (audio and voice codecs). the ac timing of audmux external pins is hence governed by the ssi module. please refer to th eir respective electrical specifications. 4.3.7 cspi electrical specifications this section describes the electr ical information of the cspi. 4.3.7.1 cspi timing figure 21 and figure 22 depict the master mode and slave mode timings of cspi, and table 30 lists the timing parameters. figure 21. cspi master mode timing diagram figure 22. cspi slave mode timing diagram cs1 cs7 cs8 cs2 cs2 cs4 cs6 cs5 cs9 cs10 sclk ssx mosi miso spi_rdy cs11 cs3 cs3 cs1 cs7 cs8 cs2 cs2 cs4 cs6 cs5 cs9 cs10 sclk ssx miso mosi cs3 cs3
electrical characteristics mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 37 4.3.8 dpll electrical specifications the three pll?s of the mcimx31 (mcu, usb, and serial pll) are all base d on same dpll design. the characteristics provided herein appl y to all of them, except where noted explicitly. the pll characteristics are provided based on measurements done for bot h sources?external clock source (ckih), and fpm (frequency pre-mul tiplier) source. 4.3.8.1 electrical specifications table 31 lists the dpll specification. table 30. cspi interf ace timing parameters id parameter symbol min max units cs1 sclk cycle time t clk 60 ? ns cs2 sclk high or low time t sw 30 ? ns cs3 sclk rise or fall t rise/fall ?7.6ns cs4 ssx pulse width t cslh 25 ? ns cs5 ssx lead time (cs setup time) t scs 25 ? ns cs6 ssx lag time (cs hold time) t hcs 25 ? ns cs7 data out setup time t smosi 5?ns cs8 data out hold time t hmosi 5?ns cs9 data in setup time t smiso 6?ns cs10 data in hold time t hmiso 5?ns cs11 spi_rdy setup time 1 1 spi_rdy is sampled internally by ipg_clk and is asynchronous to all other cspi signals. t srdy ??ns table 31. dpll specifications parameter min typ max unit comments ckih frequency 15 26 1 75 2 mhz ? ckil frequency (frequency pre-multiplier (fpm) enable mode) ? 32; 32.768, 38.4 ? khz fpm lock time 480 s. predivision factor (pd bits) 1 ? 16 ? ? pll reference frequency range after predivider 15 ? 35 mhz 15 ckih frequency/pd 35 mhz 15 fpm output/pd 35 mhz pll output frequency range: mpll and spll upll 52 190 ? 532 240 mhz ? maximum allowed reference clock phase noise. ? ? 100 ps ? frequency lock time (fol mode or non-integer mf) ? ? 398 ? cycles of divided reference clock.
mcimx31/mcimx31l technical data, rev. 4.1 38 freescale semiconductor electrical characteristics 4.3.9 emi electrical specifications this section provides electrical para metrics and timings for emi module. 4.3.9.1 nand flash contro ller interface (nfc) the nfc supports normal timing mode, using tw o flash clock cycles for one access of re and we . ac timings are provided as mu ltiplications of the cloc k cycle and fixed delay. figure 23 , figure 24 , figure 25 , and figure 26 depict the relative timing re quirements among different signals of the nfc at module level, for normal mode, and table 32 lists the timing parameters. figure 23. command latch cycle timing diagram phase lock time ? ? 100 s in addition to the frequency maximum allowed pll supply voltage ripple ? ? 25 mv f modulation < 50 khz maximum allowed pll supply voltage ripple ? ? 20 mv 50 khz < f modulation < 300 khz maximum allowed pll supply voltage ripple ? ? 25 mv f modulation > 300 khz pll output clock phase jitter ? ? 5.2 ns measured on clko pin pll output clock period jitter ? ? 420 ps measured on clko pin 1 the user or board designer must take into account that the use of a frequency other than 26 mhz would require adjustment to the dptc?dvfs table, which is incorporated into operating system code. 2 the pll reference frequency must be 35 mhz. therefore, for frequencies between 35 mhz and 70 mhz, program the predivider to divide by 2 or more. if the ckih frequency is above 70 mhz, program the predivider to 3 or more. for pd bit description, see the reference manual. table 31. dpll specifications (continued) parameter min typ max unit comments nfcle nfce nfwe nfale nfio[7:0] command nf9 nf8 nf1 nf2 nf5 nf3 nf4 nf6 nf7
electrical characteristics mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 39 figure 24. address latch cycle timing diagram figure 25. write data latch cycle timing diagram nfcle nfce nfwe nfale nfio[7:0] address nf9 nf8 nf1 nf5 nf3 nf4 nf6 nf11 nf10 nf7 nfcle nfce nfwe nfale nfio[15:0] data to nf nf9 nf8 nf1 nf5 nf3 nf6 nf11 nf10 nf7
mcimx31/mcimx31l technical data, rev. 4.1 40 freescale semiconductor electrical characteristics figure 26. read data latch cycle timing diagram table 32. nfc timing parameters 1 1 the flash clock maximum frequency is 50 mhz. id parameter symbol timing t = nfc clock cycle 2 2 subject to dpll jitter specification on table 31, "dpll specifications," on page 37 . example timing for nfc clock 33 mhz t = 30 ns unit min max min max nf1 nfcle setup time tcls t?1.0 ns ? 29 ? ns nf2 nfcle hold time tclh t?2.0 ns ? 28 ? ns nf3 nfce setup time tcs t?1.0 ns ? 29 ? ns nf4 nfce hold time tch t?2.0 ns ? 28 ? ns nf5 nf_wp pulse width twp t?1.5 ns 28.5 ns nf6 nfale setup time tals t ? 30 ? ns nf7 nfale hold time talh t?3.0 ns ? 27 ? ns nf8 data setup time tds t ? 30 ? ns nf9 data hold time tdh t?5.0 ns ? 25 ? ns nf10 write cycle time twc 2t 60 ns nf11 nfwe hold time twh t?2.5 ns 27.5 ns nf12 ready to nfre low trr 6t ? 180 ? ns nf13 nfre pulse width trp 1.5t ? 45 ? ns nf14 read cycle time trc 2t ? 60 ? ns nf15 nfre high hold time treh 0.5t?2.5 ns 12.5 ? ns nf16 data setup on read tdsr n/a 10 ? ns nf17 data hold on read tdhr n/a 0 ? ns nfcle nfce nfre nfrb nfio[15:0] data from nf nf13 nf15 nf14 nf17 nf12 nf16
electrical characteristics mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 41 note high is defined as 80% of signal value and low is defined as 20% of signal value. timing for hclk is 133 mhz and internal nfc clock (flash clock) is approximately 33 mhz (30 ns). all timings are listed according to this nfc clock frequency (multiples of nfc cl ock phases), except nf16 and nf17, which are not nfc clock related. 4.3.9.2 wireless external interface module (weim) all weim output control signals may be asserted and deasserted by internal clock related to bclk rising edge or falling edge according to corresponding assertion/nega tion control fields. a ddress always begins related to bclk falling edge but may be ended both on rising and fall ing edge in muxed mode according to control register configuration. output data begi ns related to bclk rising edge except in muxed mode where both rising and falling edge ma y be used according to control regi ster configurati on. input data, ecb and dtack all captured according to bclk rising edge time. figure 27 depicts the timing of the weim module, and table 33 lists the timing parameters.
mcimx31/mcimx31l technical data, rev. 4.1 42 freescale semiconductor electrical characteristics figure 27. weim bus timing diagram table 33. weim bus timing parameters id parameter min max unit we1 clock fall to address valid ?0.5 2.5 ns we2 clock rise/fall to address invalid ?0.5 5 ns we3 clock rise/fall to cs [x] valid ?3 3 ns we4 clock rise/fall to cs [x] invalid ?3 3 ns we5 clock rise/fall to rw valid ?3 3 ns we6 clock rise/fall to rw invalid ?3 3 ns we7 clock rise/fall to oe valid ?3 3 ns we1 we2 we3 we4 we5 we6 we7 we8 we9 we10 we11 we12 we13 we14 we16 we15 we18 we17 we20 we19 we21 we22 we23 bclk address cs [x] rw oe eb [x] lba output data bclk input data weim outputs timing weim inputs timing ecb dtack ...
electrical characteristics mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 43 note high is defined as 80% of signal value and low is defined as 20% of signal value. test conditions: load capacitance, 25 pf . recommended drive strength for all controls, address, and bclk is max drive. figure 28 , figure 29 , figure 30 , figure 31 , figure 32 , and figure 33 depict some examples of basic weim accesses to external memory devi ces with the timing parameters mentioned in table 33 for specific control parameter settings. we8 clock rise/fall to oe invalid ?3 3 ns we9 clock rise/fall to eb [x] valid ?3 3 ns we10 clock rise/fall to eb [x] invalid ?3 3 ns we11 clock rise/fall to lba valid ?3 3 ns we12 clock rise/fall to lba invalid ?3 3 ns we13 clock rise/fall to output data valid ?2.5 4 ns we14 clock rise to output data invalid ?2.5 4 ns we15 input data valid to clock rise, fce=0 fce=1 8 2.5 ? ns we16 clock rise to input data invalid, fce=0 fce=1 ?2 ?2 ? ns we17 ecb setup time, fce=0 fce=1 6.5 3.5 ? ns we18 ecb hold time, fce=0 fce=1 ?2 2 ? ns we19 dtack setup time 1 0?ns we20 dtack hold time 1 4.5 ? ns we21 bclk high level width 2, 3 ? t/2?3 ns we22 bclk low level width 2, 3 ? t/2?3 ns we23 bclk cycle time 2 15 ? ns 1 applies to rising edge timing 2 bclk parameters are being measured from the 50% vdd. 3 the actual cycle time is derived from the ahb bus clock frequency. table 33. weim bus timing parameters (continued) id parameter min max unit
mcimx31/mcimx31l technical data, rev. 4.1 44 freescale semiconductor electrical characteristics figure 28. asynchronous memory timi ng diagram for read access?wsc=1 figure 29. asynchronous memory timing diagram for write access? wsc=1, ebwa=1, ebwn=1, lbn=1 last valid address v1 v1 bclk addr data rw lba oe eb [y] cs [x] next address we1 we2 we3 we4 we7 we8 we10 we9 we11 we12 we15 we16 last valid address v1 v1 bclk addr data rw lba oe eb [y] cs [x] next address we1 we2 we3 we4 we5 we6 we9 we10 we11 we12 we13 we14
electrical characteristics mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 45 figure 30. synchronous memory timing diagram for two non-sequential read accesses? wsc=2, sync=1, dol=0 figure 31. synchronous memory timing diagram for burst write access? bcs=1, wsc=4, sync=1, dol=0, psr=1 last valid addr address v1 address v2 v1 v1+2 v2 v2+2 bclk addr ecb data halfword halfword cs[x] rw lba oe eb [y] halfword halfword we1 we2 we4 we7 we8 we9 we10 we11 we12 we15 we15 we16 we16 we17 we17 we18 we18 we3 last valid addr bclk addr data cs [x] rw lba oe eb [y] ecb address v1 v1 v1+4 v1+12 v1+8 we9 we1 we2 we3 we4 we5 we6 we10 we11 we13 we13 we14 we14 we17 we18 we12
mcimx31/mcimx31l technical data, rev. 4.1 46 freescale semiconductor electrical characteristics figure 32. muxed a/d mode timing diagram for asynchronous write access? wsc=7, lba=1, lbn=1, lah=1 figure 33. muxed a/d mode timing diag ram for asynchronous read access? wsc=7, lba=1, lbn=1, lah=1, oea=7 4.3.9.3 esdctl electrical specifications figure 34 , figure 35 , figure 36 , figure 37 , figure 38 , and figure 39 depict the timings pertaining to the esdctl module, which interfaces mobile ddr or sdr sdram. table 34 , table 35 , table 36 , table 37 , table 38 , and table 39 list the timing parameters. write bclk addr/ rw lba oe eb [y] cs [x] address v1 write data last valid addr m_data we1 we2 we3 we4 we6 we5 we9 we10 we11 we12 we13 we14 bclk addr/ rw lba oe eb [y] cs [x] address v1 read data last valid addr m_data we2 we3 we4 we11 we12 we7 we8 we9 we10 we15 we16 we1
electrical characteristics mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 47 figure 34. sdram read cycle timing diagram table 34. ddr/sdr sdram re ad cycle timing parameters id parameter symbol min max unit sd1 sdram clock high-level width tch 3.4 4.1 ns sd2 sdram clock low-level width tcl 3.4 4.1 ns sd3 sdram clock cycle time tck 7.5 ? ns sd4 cs, ras, cas, we, dqm, cke setup time tcms 2.0 ? ns sd5 cs, ras, cas, we, dqm, cke hold time tcmh 1.8 ? ns sd6 address setup time tas 2.0 ? ns sd7 address hold time tah 1.8 ? ns sd8 sdram access time tac ? 6.47 ns sdclk we addr dq dqm col/ba data cs cas ras note: cke is high during the read/write cycle. sd4 sd1 sd3 sd2 sd4 sd4 sd4 sd4 sd5 sd5 sd5 sd5 sd5 sd6 sd7 sd10 sd8 sd9 sdclk row/ba
mcimx31/mcimx31l technical data, rev. 4.1 48 freescale semiconductor electrical characteristics note sdr sdram clk parameters are being measured from the 50% point?that is, high is defined as 50% of signal value and low is defined as 50% of signal value. sd1 + sd2 does not exceed 7.5 ns for 133 mhz. the timing parameters are similar to the ones used in sdram data sheets?that is, table 34 indicates sdram requireme nts. all output signals are driven by the esdctl at the negative edge of sdclk and the parameters are measured at maximum memory frequency. sd9 data out hold time 1 toh 1.8 ? ns sd10 active to read/write command period trc 10 ? clock 1 timing parameters are relevant only to sdr sdram. for the specific ddr sdram data re lated timing parameters, see ta bl e 3 8 and ta b l e 3 9 . table 34. ddr/sdr sdram read cycl e timing parameters (continued) id parameter symbol min max unit
electrical characteristics mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 49 figure 35. sdr sdram write cycle timing diagram table 35. sdr sdram wr ite timing parameters id parameter symbol min max unit sd1 sdram clock high-level width tch 3.4 4.1 ns sd2 sdram clock low-level width tcl 3.4 4.1 ns sd3 sdram clock cycle time tck 7.5 ? ns sd4 cs, ras, cas, we, dqm, cke setup time tcms 2.0 ? ns sd5 cs, ras, cas, we, dqm, cke hold time tcmh 1.8 ? ns sd6 address setup time tas 2.0 ? ns sd7 address hold time tah 1.8 ? ns sd11 precharge cycle period 1 trp 1 4 clock sd12 active to read/write command delay 1 trcd 1 8 clock cs cas we ras addr dq dqm ba row / ba col/ba data sd4 sd4 sd4 sd4 sd5 sd5 sd5 sd5 sd7 sd6 sd12 sd13 sd14 sd11 sdclk sd1 sd3 sd2 sdclk
mcimx31/mcimx31l technical data, rev. 4.1 50 freescale semiconductor electrical characteristics note sdr sdram clk parameters are being measured from the 50% point?that is, high is defined as 50% of signal value and low is defined as 50% of signal value. the timing parameters are similar to the ones used in sdram data sheets?that is, table 35 indicates sdram requireme nts. all output signals are driven by the esdctl at the negative edge of sdclk and the parameters are measured at maximum memory frequency. figure 36. sdram refresh timing diagram sd13 data setup time tds 2.0 ? ns sd14 data hold time tdh 1.3 ? ns 1 sd11 and sd12 are determined by sdram controller register settings. table 36. sdram refresh timing parameters id parameter symbol min max unit sd1 sdram clock high-level width tch 3.4 4.1 ns sd2 sdram clock low-level width tcl 3.4 4.1 ns table 35. sdr sdram write timi ng parameters (continued) id parameter symbol min max unit cs cas we ras addr ba row/ba sd6 sd7 sd11 sd10 sd10 sdclk sd1 sd2 sdclk sd3
electrical characteristics mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 51 note sdr sdram clk parameters are being measured from the 50% point?that is, high is defined as 50% of signal value and low is defined as 50% of signal value. the timing parameters are similar to the ones used in sdram data sheets?that is, table 36 indicates sdram requireme nts. all output signals are driven by the esdctl at the negative edge of sdclk and the parameters are measured at maximum memory frequency. sd3 sdram clock cycle time tck 7.5 ? ns sd6 address setup time tas 1.8 ? ns sd7 address hold time tah 1.8 ? ns sd10 precharge cycle period 1 trp 1 4 clock sd11 auto precharge command period 1 trc 2 20 clock 1 sd10 and sd11 are determined by sdra m controller register settings. table 36. sdram refresh timing parameters (continued) id parameter symbol min max unit
mcimx31/mcimx31l technical data, rev. 4.1 52 freescale semiconductor electrical characteristics figure 37. sdram self-refresh cycle timing diagram note the clock will continue to run unless both ckes are low. then the clock will be stopped in low state. table 37. sdram self-refre sh cycle timing parameters id parameter symbol min max unit sd16 cke output delay time tcks 1.8 ? ns sdclk cs cas ras addr ba we cke don?t care sd16 sd16
electrical characteristics mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 53 figure 38. mobile ddr sdram write cycle timing diagram note sdram clk and dqs related paramete rs are being measured from the 50% point?that is, high is defined as 50% of signal value and low is defined as 50% of signal value. the timing parameters are similar to the ones used in sdram data sheets?that is, table 38 indicates sdram requireme nts. all output signals are driven by the esdctl at the negative edge of sdclk and the parameters are measured at maximum memory frequency. table 38. mobile ddr sdram wr ite cycle timing parameters 1 1 test condition: measured using delay line 5 pr ogrammed as follows: esdcdly5[15:0] = 0x0703. id parameter symbol min max unit sd17 dq and dqm setup time to dqs tds 0.95 ? ns sd18 dq and dqm hold time to dqs tdh 0.95 ? ns sd19 write cycle dqs falling edge to sdclk output delay time. tdss 1.8 ? ns sd20 write cycle dqs falling edge to sdclk output hold time. tdsh 1.8 ? ns sdclk sdclk dqs (output) dq (output) dqm (output) data data data data data data data data dm dm dm dm dm dm dm dm sd17 sd17 sd17 sd17 sd18 sd18 sd18 sd18 sd19 sd20
mcimx31/mcimx31l technical data, rev. 4.1 54 freescale semiconductor electrical characteristics figure 39. mobile ddr sdram dq versus dqs and sdclk read cycle timing diagram note sdram clk and dqs related paramete rs are being measured from the 50% point?that is, high is defined as 50% of signal value and low is defined as 50% of signal value. the timing parameters are similar to the ones used in sdram data sheets?that is, table 39 indicates sdram requireme nts. all output signals are driven by the esdctl at the negative edge of sdclk and the parameters are measured at maximum memory frequency. 4.3.10 etm electrical specifications etm is an arm protocol. the timing specifications in this section are given as a guide for a tpa that supports traceclk frequencies up to 133 mhz. figure 40 depicts the traceclk timings of etm, and table 40 lists the timing parameters. figure 40. etm traceclk timing diagram table 39. mobile ddr sdram read cycle timing parameters id parameter symbol min max unit sd21 dqs ? dq skew (defines the data valid windo w in read cycles related to dqs). tdqsq ? 0.85 ns sd22 dqs dq hold time from dqs tqh 2.3 ? ns sd23 dqs output access time from sdclk posedge tdqsck ? 6.7 ns sdclk sdclk dqs (input) dq (input) data data data data data data data data sd23 sd21 sd22
electrical characteristics mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 55 figure 41 depicts the setup and hold require ments of the trace data pins with respect to traceclk, and table 41 lists the timing parameters. figure 41. trace data timing diagram 4.3.10.1 half-rate clocking mode when half-rate clocking is used, the trace data signals are sampled by the tp a on both the rising and falling edges of traceclk, where traceclk is ha lf the frequency of the clock shown in figure 41 . 4.3.11 fir electrical specifications fir implements asynchronous infrared protocol s (fir, mir) that are defined by irda ? (infrared data association). refer to http://www.irda .org for details on fir and mir protocols. 4.3.12 fusebox electrical specifications table 40. etm traceclk timing parameters id parameter min max unit t cyc clock period frequency dependent ? ns t wl low pulse width 2 ? ns t wh high pulse width 2 ? ns t r clock and data rise time ? 3 ns t f clock and data fall time ? 3 ns table 41. etm trace data timing parameters id parameter min max unit t s data setup 2 ? ns t h data hold 1 ? ns table 42. fusebox timing characteristics ref. num description symbol m inimum typical maximum units 1 program time for efuse 1 1 the program length is defined by the value defined in the epm _pgm_length[2:0] bits of the iim module. the value to program is based on a 32 khz clock source (4 * 1/32 khz = 125 s). t program 125 ? ? s
mcimx31/mcimx31l technical data, rev. 4.1 56 freescale semiconductor electrical characteristics 4.3.13 i 2 c electrical specifications this section describes the elec trical information of the i 2 c module. 4.3.13.1 i 2 c module timing figure 42 depicts the timing of i 2 c module. table 43 lists the i 2 c module timing parameters where the i/o supply is 2.7 v. 1 figure 42. i 2 c bus timing diagram table 43. i 2 c module timing parameters?i 2 c pin i/o supply=2.7 v id parameter standard mode fast mode unit min max min max ic1 i2clk cycle time 10 ? 2.5 ? s ic2 hold time (repeated) start condition 4.0 ? 0.6 ? s ic3 set-up time for stop condition 4.0 ? 0.6 ? s ic4 data hold time 0 1 1 a device must internally provide a hold time of at least 300 ns for i2dat signal in order to bridge the undefined region of the falling edge of i2clk. 3.45 2 2 the maximum hold time has to be met only if the device does not stretch the low period (id ic6) of the i2clk signal. 0 1 0.9 2 s ic5 high period of i2clk clock 4.0 ? 0.6 ? s ic6 low period of the i2clk clock 4.7 ? 1.3 ? s ic7 set-up time for a repeated start condition 4.7 ? 0.6 ? s ic8 data set-up time 250 ? 100 3 3 a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement of set-up time (id ic7) of 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the i2clk signal. if such a device does stretch the low period of the i2clk signal, it must output the next data bit to the i2dat line max_rise_t ime (id no ic10) + data_setup_time (id no ic8) = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the i2clk line is released. ?ns ic9 bus free time between a stop and start condition 4.7 ? 1.3 ? s ic10 rise time of both i2dat and i2clk signals ? 1000 20+0.1c b 4 4 c b = total capacitance of one bus line in pf. 300 ns ic11 fall time of both i2dat and i2clk signals ? 300 20+0.1c b 4 300 ns ic12 capacitive load for each bus line (c b ) ? 400 ? 400 pf ic10 ic11 ic9 ic2 ic8 ic4 ic7 ic3 ic6 ic10 ic5 ic11 start stop start start i2dat i2clk ic1
electrical characteristics mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 57 4.3.14 ipu?sensor interfaces 4.3.14.1 supported camera sensors table 44 lists the known supported camera se nsors at the time of publication. 4.3.14.2 functional description there are three timing modes supported by the ipu. 4.3.14.2.1 pseudo bt.656 video mode smart camera sensors, which incl ude imaging processing, usually suppor t video mode transfer. they use an embedded timing syntax to replace the sen sb_vsync and sensb_hsync signals. the timing syntax is defined by the bt.656 standard. this operation mode follows the re commendations of itu bt.656 specif ications. the only control signal used is sensb_pix_clk. start-of-f rame and active-line si gnals are embedded in the data stream. an active line starts wi th a sav code and ends with a eav code. in some cases, digital bl anking is inserted in between eav and sav code. the csi decodes and filters out the timi ng-coding from the da ta stream, thus recovering sensb_vsync and sensb_h sync signals for internal use. table 44. supported camera sensors 1 1 freescale semiconductor does not recommend one supplier over another and in no way suggests that these are the only camera suppliers. vendor model conexant cx11646, cx20490 2 , cx20450 2 2 these sensors not validated at time of publication. agilant hdcp?2010, adcs?1021 2 , adcs?1021 2 toshiba tc90a70 icmedia icm202a, icm102 2 imagic im8801 transchip tc5600, tc5600j, tc5640, tc5700, tc6000 fujitsu mb86s02a micron mi?soc?0133 matsushita mn39980 stmicro w6411, w6500, w6501 2 , w6600 2 , w6552 2 , stv0974 2 omnivision ov7620, ov6630 sharp lz0p3714 (ccd) motorola mc30300 (python) 2 , scm20014 2 , scm20114 2 , scm22114 2 , scm20027 2 national semiconductor lm9618 2
mcimx31/mcimx31l technical data, rev. 4.1 58 freescale semiconductor electrical characteristics 4.3.14.2.2 gated clock mode the sensb_vsync, sensb_hsync, and sensb_pix_clk signals are used in this mode. see figure 43 . figure 43. gated clock mode timing diagram a frame starts with a rising edge on sensb_vsync (all the timings corr espond to straight polarity of the corresponding signals). then sensb_ hsync goes to high and hold for the entire line. pixel clock is valid as long as sensb_hsync is high. data is latched at the rising edge of the valid pixel clocks. sensb_hsync goes to low at the end of line. pixel clocks then become invalid and the csi stops receiving data from the stream. fo r next line the sensb_hsync timi ng repeats. for next frame the sensb_vsync timing repeats. 4.3.14.2.3 non-gated clock mode the timing is the same as the gated-clock mode (described in section 4.3.14.2.2, ?gated clock mode ?), except for the sensb_hsync sign al, which is not used. see figure 44 . all incoming pixel clocks are valid and will cause data to be latched into the in put fifo. the sensb_pix_clk signal is inactive (states low) until valid data is going to be transmitted over the bus. figure 44. non-gated clock mode timing diagram sensb_vsync sensb_hsync sensb_pix_clk sensb_data[9:0] invalid 1st byte n+1th frame invalid 1st byte nth frame active line start of frame sensb_vsync sensb_pix_clk sensb_data[7:0] invalid 1st byte n+1th frame invalid 1st byte nth frame start of frame
electrical characteristics mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 59 the timing described in figure 44 is that of a motorola sensor. some other sensors may have a slightly different timing. the csi can be programmed to support rising/fal ling-edge triggere d sensb_vsync; active-high/low sensb_hsync ; and rising/falling-edge triggered sensb_pix_clk. 4.3.14.3 electrical characteristics figure 45 depicts the sensor interface timing, and table 45 lists the timing parameters. figure 45. sensor interface timing diagram 4.3.15 ipu ? display interfaces 4.3.15.1 supported display components table 46 lists the known supported display co mponents at the time of publication. table 45. sensor interface timing parameters 1 1 the timing specifications for figure 45 are referenced to the rising edge of sens_pix_clk when the sens_pix_clk_pol bit in th e csi_sens_conf register is cleared . when the sens_pix_clk_pol is set, the clock is inverted and all timing specifications will re main the same but are referenced to the falling edge of the clock. id parameter symbol min. max. units ip1 sensor input clock frequency fmck 0.01 133 mhz ip2 data and control setup time tsu 5 ? ns ip3 data and control holdup time thd 3 ? ns ip4 sensor output (pixel) clock frequency fpck 0.01 133 mhz sensb_mclk ip3 sensb_data, sensb_vsync, ip2 1/ip1 1/ip4 sensb_pix_clk (sensor input) (sensor output) sensb_hsync
mcimx31/mcimx31l technical data, rev. 4.1 60 freescale semiconductor electrical characteristics 4.3.15.2 synchronous interfaces 4.3.15.2.1 interface to active matrix tft lcd panels, func tional description figure 46 depicts the lcd interface timi ng for a generic active matrix color tft panel. in this figure signals are shown with negative polarity. the sequence of events fo r active matrix interface timing is: ? dispb_d3_clk latches data into the panel on its negative edge (when positive polarity is selected). in active mode, di spb_d3_clk runs continuously. ? dispb_d3_hsync causes the panel to start a new line. ? dispb_d3_vsync causes the panel to start a ne w frame. it always encompasses at least one hsync pulse. table 46. supported display components 1 1 freescale semiconductor does not recommend one supplier over another and in no way sugges ts that these are the only display component suppliers. type vendor model tft displays (memory-less) sharp (hr-tft super mobile lcd family) lq035q7 db02, lm019lc1sxx samsung (qcif and qvga tft modules for mobile phones) lts180s1-hf1, lts180s3-hf1, lts350q1-pe1, lts350q1-pd1, lts220q1-he1 2 2 these display components not valid ated at time of publication. toshiba (ltm series) ltm022p806 2 , ltm04c380k 2 , ltm018a02a 2 , ltm020p332 2 , ltm021p337 2 , ltm019p334 2 , ltm022a783 2 , ltm022a05zz 2 nec nl6448bc20-08e, nl8060bc31-27 display controllers epson s1 d15xxx series, s1d19xxx se ries, s1d13713, s1d13715 solomon systech ssd1301 (oled), ssd1828 (ldcd) hitachi hd66766, hd66772 ati w2300 smart display modules epson l1f10043 t 2 , l1f10044 t 2 , l1f10045 t 2 , l2d22002 2 , l2d20014 2 , l2f50032 2 , l2d25001 t 2 hitachi 120 160 65k/4096 c-stn (# 3284 ltd-1398-2) based on hd 66766 controller densitron europe ltd all displays with mpu 80/68k series interface and serial peripheral interface sharp lm019lc1sxx sony acx506akm digital video encoders (for tv) analog devices adv7174/7179 crystal (cirrus logic) cs49xx series focus fs453/4
electrical characteristics mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 61 ? dispb_d3_drdy acts like an output enable signa l to the crt display. this output enables the data to be shifted onto the display. when di sabled, the data is invalid and the trace is off. figure 46. interface timing diagram for tft (active matrix) panels 4.3.15.2.2 interface to active matrix tft lcd panels, electri cal characteristics figure 47 depicts the horizontal timing (ti ming of one line), including bot h the horizontal sync pulse and the data. all figure parameters shown are programmable. the timing images correspond to inverse polarity of the dispb_d3_clk signal and active-low polarity of the dispb _d3_hsync, dispb_d3_vsync and dispb_d3_drdy signals. figure 47. tft panels timing di agram?horizontal sync pulse figure 48 depicts the vertical timing (timing of one frame). all figure parameters shown are programmable. dispb_d3_clk 123 m m-1 dispb_d3_hsync dispb_d3_vsync dispb_d3_hsync line 1 line 2 line 3 line 4 line n-1 line n dispb_d3_drdy dispb_d3_data dispb_d3_hsync dispb_d3_drdy dispb_d3_data dispb_d3_clk ip7 ip9 ip10 ip8 start of line ip5 ip6
mcimx31/mcimx31l technical data, rev. 4.1 62 freescale semiconductor electrical characteristics figure 48. tft panels timing diagram?vertical sync pulse table 47 shows timing parameters of signals presented in figure 47 and figure 48 . table 47. synchronous display interface timing parameters?pixel level id parameter symbol value units ip5 display interface clock period tdicp tdicp 1 1 display interface clock period immediate value. display interface clock period average value. ns ip6 display pixel clock period tdpcp (disp3_if_clk_cnt_d+1) * tdicp ns ip7 screen width tsw (screen_width+1) * tdpcp ns ip8 hsync width thsw (h_sync_width+1) * tdpcp ns ip9 horizontal blank interval 1 thbi1 bgxp * tdpcp ns ip10 horizontal blank interval 2 thbi2 (screen_width ? bgxp ? fw) * tdpcp ns ip11 hsync delay thsd h_sync_delay * tdpcp ns ip12 screen height tsh (screen_height+1) * tsw ns ip13 vsync width tvsw if v_sync_width_l = 0 than (v_sync_width+1) * tdpcp else (v_sync_width+1) * tsw ns ip14 vertical blank interval 1 tvbi1 bgyp * tsw ns ip15 vertical blank interval 2 tvbi2 (screen_height ? bgyp ? fh) * tsw ns ip14 dispb_d3_vsync dispb_d3_hsync dispb_d3_drdy start of frame end of frame ip12 ip15 ip13 ip11 tdicp t hsp_clk disp3_if_clk_per_wr hsp_clk_period ----------------------------------------------------------------- - ? for integer disp3_if_clk_per_wr hsp_clk_period ----------------------------------------------------------------- - , t hsp_clk floor disp3_if_clk_per_wr hsp_clk_period ----------------------------------------------------------------- - 0.5 0.5 + ?? ?? ? for fractional disp3_if_clk_per_wr hsp_clk_period ----------------------------------------------------------------- - , ? ? ? ? ? ? ? = tdicp t hsp_clk disp3_if_clk_per_wr hsp_clk_period ----------------------------------------------------------------- - ? =
electrical characteristics mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 63 note hsp_clk is the high-speed port clock, which is the input to the image processing unit (ipu). its frequency is controlled by the clock control module (ccm) settings. the hsp_clk frequency must be greater than or equal to the ahb clock frequency. the screen_width, screen_h eight, h_sync_width, v_sy nc_width, bgxp, bgyp and v_sync_width_l parameters are programme d via the sdc_hor_conf, sdc_ver_conf, sdc_bg_pos registers. the fw and fh parame ters are programmed for the corresponding dma channel. the disp3_if_clk_per_wr, hsp_clk_ period and disp3_if_clk_cnt_d parameters are programmed via the di_disp3_time_c onf, di_hsp_clk_per and di_disp_acc_cc registers. figure 49 depicts the synchronous display in terface timing for access level, and table 48 lists the timing parameters. the disp3_if_clk_do wn_wr and disp3_if_clk_up_wr parameters are set via the di_disp3_time_conf register. figure 49. synchronous display interface timing diagram?access level table 48. synchronous display interface timing parameters?access level id parameter symbol min typ 1 1 the exact conditions have not been finalized, but will likely matc h the current customer requirem ent for their specific display . these conditions may be device specific. max units ip16 display interface clock low time tckl tdicd?tdicu?1.5 tdicd 2 ?tdicu 3 tdicd?tdicu+1.5 ns ip17 display interface clock high time tckh tdicp?tdicd+tdicu?1.5 tdicp?tdicd+tdicu tdicp?tdicd+tdicu+1.5 ns ip18 data setup time tdsu tdicd?3.5 tdicu ? ns ip19 data holdup time tdhd tdicp?tdicd?3.5 tdicp?tdicu ? ns ip20 control signals setup time to display interface clock tcsu tdicd?3.5 tdicu ? ns ip19 dispb_d3_clk dispb_data ip18 ip20 dispb_d3_vsync ip17 ip16 dispb_d3_drdy dispb_d3_hsync other controls
mcimx31/mcimx31l technical data, rev. 4.1 64 freescale semiconductor electrical characteristics 4.3.15.3 interface to sharp hr-tft panels figure 50 depicts the sharp hr-tft panel interface timing, and table 49 lists the timing parameters. the cls_rise_delay, cls_fall_delay, ps_fall_delay, ps_rise_delay, rev_toggle_delay parameters are de fined in the sdc_sharp_conf_1 and sdc_sharp_conf_2 registers. for other sharp interface timing characteristics, refer to section 4.3.15.2.2, ?interface to ac tive matrix tft lcd panels , electrical characteristics . ? the timing images correspond to straight polarity of the sharp signals. figure 50. sharp hr-tft panel interface timing diagram?pixel level 2 display interface clock down time 3 display interface clock up time where ceil(x) rounds the elements of x to the nearest integers towards infinity. tdicd 1 2 -- - t hsp_clk ceil 2 disp3_if_clk_down_wr ? hsp_clk_period -------------------------------------------------------------------------------- - ? = tdicu 1 2 -- - t hsp_clk ceil 2 disp3_if_clk_up_wr ? hsp_clk_period --------------------------------------------------------------------- - ? = d1 d2 dispb_d3_clk dispb_d3_data dispb_d3_spl dispb_d3_hsync dispb_d3_cls dispb_d3_ps dispb_d3_rev 1 dispb_d3_clk period ip26 d320 horizontal timing ip22 ip23 ip25 ip21 ip24 example is drawn with fw+1=320 pixel/line, fh+1=240 lines. spl pulse width is fixed and align ed to the first data of the line. rev toggles every hsync period.
electrical characteristics mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 65 4.3.15.4 synchronous interface to dual-port smart displays functionality and electrical characteristics of the synchronous interf ace to dual-port smart displays are identical to parameters of the synchronous interface. see section 4.3.15.2.2, ?interface to active matrix tft lcd panels, electrical characteristics .? 4.3.15.4.1 interface to a tv encoder, functional description the interface has an 8-bit data bus, transferring a single 8-bit value (y/u/v) in each cycle. the bits d7?d0 of the value are mapped to bits ld17?ld10 of the data bus, respectively. figure 51 depicts the interface timing, ? the frequency of the clock disp b_d3_clk is 27 mhz (within 10%). ? the dispb_d3_hsync, dispb_d 3_vsync and dispb_d3_drdy signals are active low. ? the transition to the next row is marked by the negative edge of the dispb_d3_hsync signal. it remains low for a single clock cycle. ? the transition to the next field/frame is mark ed by the negative edge of the dispb_d3_vsync signal. it remains low for at least one clock cycle. ? at a transition to an odd field (of the next frame), the negative edges of dispb_d3_vsync and dispb_d3_hsync coincide. ? at a transition to an even field (of the same frame), they do not coincide. ? the active intervals?during wh ich data is transferred?are ma rked by the dispb_d3_hsync signal being high. table 49. sharp synchronous display interface timing parameters?pixel level id parameter symbol value units ip21 spl rise time tsplr (bgxp ? 1) * tdpcp ns ip22 cls rise time tclsr cls_rise_delay * tdpcp ns ip23 cls fall time tclsf cls_fall_delay * tdpcp ns ip24 cls rise and ps fall time tpsf ps_fall_delay * tdpcp ns ip25 ps rise time tpsr ps_rise_delay * tdpcp ns ip26 rev toggle time trev rev_toggle_delay * tdpcp ns
mcimx31/mcimx31l technical data, rev. 4.1 66 freescale semiconductor electrical characteristics figure 51. tv encoder interface timing diagram dispb_d3_clk dispb_d3_hsync dispb_data dispb_d3_vsync cb y cr cb y cr y pixel data timing line and field timing - ntsc even field odd field odd field even field 624 621 311 308 line and field timing - pal dispb_d3_hsync dispb_d3_drdy dispb_d3_vsync dispb_d3_hsync dispb_d3_drdy dispb_d3_vsync even field odd field odd field even field 1 523 262 261 dispb_d3_drdy dispb_d3_hsync dispb_d3_drdy dispb_d3_vsync dispb_d3_hsync dispb_d3_vsync 524 525 2 3 4 10 263 264 265 266 267 268 269 273 622 623 625 1 2 23 309 310 312 313 314 336 56 34 316 315 dispb_d3_drdy
electrical characteristics mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 67 4.3.15.4.2 interface to a tv encoder, electrical characteristics the timing characteristics of the tv encoder in terface are identical to the synchronous display characteristics. see section 4.3.15.2.2, ?interface to active matrix tft lcd panels, electrical characteristics .? 4.3.15.5 asynchronous interfaces 4.3.15.5.1 parallel interfaces, functional description the ipu supports the following asynchronous parallel interfaces: ? system 80 interface ? type 1 (sampling with the ch ip select signal) with and without byte enable signals. ? type 2 (sampling with the read and write signals) with and without byte enable signals. ? system 68k interface ? type 1 (sampling with the ch ip select signal) with or without byte enable signals. ? type 2 (sampling with the read and write signals) with or without byte enable signals. for each of four system interf aces, there are three burst modes: 1. burst mode without a separate clock. the burst length is defined by the corresponding parameters of the idmac (when data is transferred from th e system memory) of by the hburst signal (when the mcu directly accesses the disp lay via the slave ahb bus). for system 80 and system 68k type 1 interfaces, data is sampled by the cs signal and other control si gnals changes only when transfer direction is changed during the burs t. for type 2 interfaces, data is sampled by the wr/rd signals (system 80) or by the enable si gnal (system 68k) and the cs signa l stays active during the whole burst. 2. burst mode with the separate clock dispb_bc lk. in this mode, data is sampled with the dispb_bclk clock. the cs signal stays active dur ing whole burst transfer. other controls are changed simultaneously with data when the bus state (read, write or wait) is altered. the cs signals and other controls move to non-acti ve state after burst has been completed. 3. single access mode. in this mode, slave ahb and dma burst are broken to single accesses. the data is sampled with cs or other controls acco rding the interface type as described above. all controls (including cs) become non-active for one display interface clock after each access. this mode corresponds to the ati single access mode. both system 80 and system 68k in terfaces are supported for all desc ribed modes as depicted in figure 52 , figure 53 , figure 54 , and figure 55 . these timing images corres pond to active-low dispb_d#_cs, dispb_d#_wr and di spb_d#_rd signals. additionally, the ipu allows a programmable pause be tween two burst. the pause is defined in the hsp_clk cycles. it allows to avoid timing violat ion between two sequential bursts or two accesses to different displays. the range of this pause is from 4 to 19 hsp_clk cycles.
mcimx31/mcimx31l technical data, rev. 4.1 68 freescale semiconductor electrical characteristics figure 52. asynchronous parallel system 80 interface (type 1) burst mode timing diagram dispb_d#_cs dispb_par_rs dispb_wr dispb_rd dispb_data dispb_bclk dispb_d#_cs dispb_par_rs dispb_wr dispb_rd dispb_data dispb_d#_cs dispb_par_rs dispb_wr dispb_rd dispb_data burst access mode with sampling by cs signal burst access mode with sampling by separate burst clock (bclk) single access mode (all control signals ar e not active for one display interface clock after each display access)
electrical characteristics mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 69 figure 53. asynchronous parallel system 80 interface (type 2) burst mode timing diagram dispb_d#_cs dispb_par_rs dispb_wr dispb_rd dispb_data dispb_bclk dispb_d#_cs dispb_par_rs dispb_wr dispb_rd dispb_data dispb_d#_cs dispb_par_rs dispb_wr dispb_rd dispb_data burst access mode with sampling by wr/rd signals burst access mode with sampling by separate burst clock (bclk) single access mode (all control signals ar e not active for one display interface clock after each display access)
mcimx31/mcimx31l technical data, rev. 4.1 70 freescale semiconductor electrical characteristics figure 54. asynchronous parallel system 68k interface (type 1) burst mode timing diagram dispb_d#_cs dispb_wr dispb_rd dispb_data dispb_bclk dispb_d#_cs dispb_par_rs dispb_wr dispb_rd dispb_data dispb_d#_cs dispb_wr dispb_rd dispb_data (read/write) (enable) dispb_par_rs dispb_par_rs (read/write) (enable) (read/write) (enable) burst access mode with sampling by cs signal burst access mode with sampling by separate burst clock (bclk) single access mode (all control signals ar e not active for one display interface clock after each display access)
electrical characteristics mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 71 figure 55. asynchronous parallel system 68k interface (type 2) burst mode timing diagram display read operation can be performed with wait st ates when each read access takes up to four display interface clock cycles according to th e disp0_rd_wait_st parameter in the di_disp0_time_conf_3, di_disp1_time_con f_3, di_disp2_time_conf_3 registers. figure 56 shows timing of the parallel interface with read wait states. dispb_d#_cs dispb_par_rs dispb_wr dispb_rd dispb_data dispb_bclk dispb_d#_cs dispb_par_rs dispb_wr dispb_rd dispb_data dispb_d#_cs dispb_par_rs dispb_wr dispb_rd dispb_data (read/write) (enable) (read/write) (enable) (read/write) (enable) burst access mode with sampling by enable signal burst access mode with sampling by separate burst clock (bclk) single access mode (all control signals ar e not active for one display interface clock after each display access)
mcimx31/mcimx31l technical data, rev. 4.1 72 freescale semiconductor electrical characteristics figure 56. parallel interface ti ming diagram?read wait states 4.3.15.5.2 parallel interfaces , electrical characteristics figure 57 , figure 59 , figure 58 , and figure 60 depict timing of asynchronous parallel interfaces based on the system 80 and system 68k interfaces. table 50 lists the timing parameters at display access level. all timing images are based on active low control signa ls (signals polarity is controlled via the di_disp_sig_pol register). write operation read operation dispb_d#_cs dispb_rd dispb_wr dispb_par_rs dispb_d#_cs dispb_rd dispb_wr dispb_par_rs dispb_data dispb_d#_cs dispb_rd dispb_wr dispb_par_rs dispb_data dispb_data disp0_rd_wait_st=00 disp0_rd_wait_st=01 disp0_rd_wait_st=10
electrical characteristics mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 73 figure 57. asynchronous parallel system 80 interface (type 1) timing diagram ip28, ip27 read data ip32, ip30 ip37 ip38 dispb_par_rs dispb_data dispb_data dispb_wr (write_l) (input) (output) ip35, ip33 ip36, ip34 ip31, ip29 ip40 ip39 ip46,ip44 ip47 ip45, ip43 ip42, ip41 dispb_rd (read_l) dispb_d#_cs dispb_data[16] dispb_data[17] read point (write_h) (read_h)
mcimx31/mcimx31l technical data, rev. 4.1 74 freescale semiconductor electrical characteristics figure 58. asynchronous parallel system 80 interface (type 2) timing diagram ip28, ip27 read data ip32, ip30 dispb_par_rs dispb_data dispb_data dispb_wr (write_l) (input) (output) ip36, ip34 ip31, ip29 ip40 ip39 ip47 ip45, ip43 ip42, ip41 dispb_rd (read_l) dispb_d#_cs dispb_data[16] dispb_data[17] (write_h) (read_h) ip38 ip35, ip33 ip37 read point ip46,ip44
electrical characteristics mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 75 figure 59. asynchronous parallel system 68k interface (type 1) timing diagram ip28, ip27 read data ip32, ip30 ip37 ip38 dispb_par_rs dispb_data dispb_data dispb_wr (input) (output) ip35,ip33 ip36, ip34 ip31, ip29 ip40 ip39 ip47 ip45, ip43 ip42, ip41 dispb_rd (enable_l) dispb_d#_cs (read/write) dispb_data[17] (enable_h) read point ip46,ip44
mcimx31/mcimx31l technical data, rev. 4.1 76 freescale semiconductor electrical characteristics figure 60. asynchronous parallel system 68k interface (type 2) timing diagram table 50. asynchronous parallel interface timing parameters?access level id parameter symbol min. typ. 1 max. units ip27 read system cycle time tcycr tdicpr?1.5 tdicpr 2 tdicpr+1.5 ns ip28 write system cycle ti me tcycw tdicpw?1.5 tdicpw 3 tdicpw+1.5 ns ip29 read low pulse width trl tdicdr?tdicur?1.5 tdicdr 4 ?tdicur 5 tdicdr?tdicur+1.5 ns ip30 read high pulse width trh tdicpr ?tdicdr+tdicur?1.5 tdicpr?tdicdr+ tdicur tdicpr?tdicdr+tdicur+1.5 ns ip31 write low pulse width twl tdicdw?tdicuw?1.5 tdicdw 6 ?tdicuw 7 tdicdw?tdicuw+1.5 ns ip32 write high pulse width twh tdicpw?tdicdw+ tdicuw?1.5 tdicpw?tdicdw+ tdicuw tdicpw?tdicdw+ tdicuw+1.5 ns ip33 controls setup time for read tdcsr tdicur?1.5 tdicur ? ns ip34 controls hold time for read tdchr tdicpr?tdicdr?1.5 tdicpr?tdicdr ? ns ip35 controls setup time for write tdcsw tdicuw?1.5 tdicuw ? ns ip28, ip27 read data ip32, ip30 ip37 ip38 dispb_par_rs dispb_data dispb_data dispb_wr (input) (output) ip35,ip33 ip36, ip34 ip31, ip29 ip40 ip39 ip45, ip43 ip42, ip41 dispb_rd (enable_l) dispb_d#_cs (read/write) dispb_data[17] (enable_h) read point ip46,ip44 ip47
electrical characteristics mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 77 ip36 controls hold time for write tdchw tdicpw?tdicdw?1.5 tdicpw?tdicdw ? ns ip37 slave device data delay 8 tracc 0 ? tdrp 9 ?tlbd 10 ?tdicur?1.5 ns ip38 slave device data hold time 8 troh tdrp?tlbd?tdicdr+1.5 ? tdicpr?tdicdr?1.5 ns ip39 write data setup time tds tdicdw?1.5 tdicdw ? ns ip40 write data hold time tdh tdicpw?tdicdw?1.5 tdicpw?tdicdw ? ns ip41 read period 2 tdicpr tdicpr?1.5 tdicpr tdicpr+1.5 ns ip42 write period 3 tdicpw tdicpw?1.5 tdicpw tdicpw+1.5 ns ip43 read down time 4 tdicdr tdicdr?1.5 tdicdr tdicdr+1.5 ns ip44 read up time 5 tdicur tdicur?1.5 tdicur tdicur+1.5 ns ip45 write down time 6 tdicdw tdicdw?1.5 tdicdw tdicdw+1.5 ns ip46 write up time 7 tdicuw tdicuw?1.5 tdicuw tdicuw+1.5 ns ip47 read time point 9 tdrp tdrp?1.5 tdrp tdrp+1.5 ns 1 the exact conditions have not been finalized, but will likely match the current customer requiremen t for their specific display . these conditions may be device specific. 2 display interface clock period value for read: 3 display interface clock period value for write: 4 display interface clock down time for read: 5 display interface clock up time for read: 6 display interface clock down time for write: 7 display interface clock up time for write: 8 this parameter is a requirement to the display connected to the ipu 9 data read point 10 loopback delay tlbd is the cumulative propagation delay of read controls and read data. it incl udes an ipu output delay, a device-level output delay, board delays, a device-level input delay, an ipu input delay. this value is device specific. table 50. asynchronous parallel interface timing parameters?access level (continued) id parameter symbol min. typ. 1 max. units tdicpr t hsp_clk ceil ? disp#_if_clk_per_rd hsp_clk_period ---------------------------------------------------------------- = tdicpw t hsp_clk ceil ? disp#_if_clk_per_wr hsp_clk_period ----------------------------------------------------------------- - = tdicdr 1 2 -- - t hsp_clk ceil 2 disp#_if_clk_down_rd ? hsp_clk_period ------------------------------------------------------------------------------- ? = tdicur 1 2 -- - t hsp_clk ceil 2 disp#_if_clk_up_rd ? hsp_clk_period -------------------------------------------------------------------- ? = tdicdw 1 2 -- - t hsp_clk ceil 2 disp#_if_clk_down_wr ? hsp_clk_period -------------------------------------------------------------------------------- - ? = tdicuw 1 2 -- - t hsp_clk ceil 2 disp#_if_clk_up_wr ? hsp_clk_period --------------------------------------------------------------------- - ? = tdrp t hsp_clk ceil disp#_read_en hsp_clk_period -------------------------------------------------- ? =
mcimx31/mcimx31l technical data, rev. 4.1 78 freescale semiconductor electrical characteristics the disp#_if_clk_per_wr, disp#_if_clk_per_rd, hsp_clk_period, disp#_if_clk_down_wr, disp#_if_clk_up_wr, disp#_if_clk_down_rd, disp#_if_clk_up_rd and disp#_read_en parameters are programmed via the di_disp#_time_conf_1, di_disp#_time_con f_2 and di_hsp_clk_per registers. 4.3.15.5.3 serial interfaces , functional description the ipu supports the following typ es of asynchronous serial interfaces: ? 3-wire (with bidirectional data line) ? 4-wire (with separate data input and output lines) ? 5-wire type 1 (with sampling rs by the serial clock) ? 5-wire type 2 (with sampling rs by the chip select signal) figure 61 depicts timing of th e 3-wire serial interface. the tim ing images correspond to active-low dispb_d#_cs signal and the straight pol arity of the dispb_sd_d_clk signal. for this interface, a bidirectional data line is used outside the device. the ipu still uses separate input and output data lines (ipp_ind_dispb_sd_d and i pp_do_dispb_sd_d). the i/o mux should provide joining the internal data lines to the bidirectiona l external line according to the ipp_obe_dispb_sd_d signal provided by the ipu. each data transfer can be preceded by an optional preamble with programmable length and contents. the preamble is followed by read/write (rw) and addr ess (rs) bits. th e order of the these bits is programmable. the rw bit can be disabled. the follow ing data can consist of one word or of a whole burst. the interface parameters are controlled by the di_ser_disp1_conf and di_ser_disp2_conf registers. figure 61. 3-wire serial interface timing diagram figure 62 depicts timing of the 4-wire seria l interface. for this interface, there are separate input and output data lines both inside and outside the device. preamble dispb_d#_cs dispb_sd_d_clk dispb_sd_d rw rs input or output data d7 d6 d5 d4 d3 d2 d1 d0 1 display if clock cycle 1 display if clock cycle
electrical characteristics mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 79 figure 62. 4-wire serial interface timing diagram figure 63 depicts timing of the 5- wire serial interface (type 1). for this interface, a separate rs line is added. when a burst is transmitted within single active chip select interval, the rs can be changed at boundaries of words. preamble dispb_d#_cs dispb_sd_d_clk dispb_sd_d rw rs output data d7 d6 d5 d4 d3 d2 d1 d0 dispb_sd_d (output) (input) preamble dispb_d#_cs dispb_sd_d_clk dispb_sd_d rw rs input data dispb_sd_d d7 d6 d5 d4 d3 d2 d1 d0 (output) (input) write read 1 display if clock cycle 1 display if clock cycle 1 display if clock cycle 1 display if clock cycle
mcimx31/mcimx31l technical data, rev. 4.1 80 freescale semiconductor electrical characteristics figure 63. 5-wire serial interface (type 1) timing diagram preamble dispb_d#_cs dispb_sd_d_clk dispb_sd_d rw d7 d6 d5 d4 d3 d2 d1 d0 dispb_sd_d (output) (input) dispb_d#_cs dispb_sd_d_clk dispb_sd_d rw dispb_sd_d d7 d6 d5 d4 d3 d2 d1 d0 (output) (input) write read dispb_ser_rs dispb_ser_rs 1 display if clock cycle 1 display if clock cycle output data 1 display if clock cycle 1 display if clock cycle preamble input data
electrical characteristics mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 81 figure 64 depicts timing of the 5- wire serial interface (type 2). for this interface, a separate rs line is added. when a burst is transmitted within single active chip select interval, the rs can be changed at boundaries of words. figure 64. 5-wire serial interface (type 2) timing diagram preamble dispb_d#_cs dispb_sd_d_clk dispb_sd_d rw output data d7 d6 d5 d4 d3 d2 d1 d0 dispb_sd_d (output) (input) preamble dispb_d#_cs dispb_sd_d_clk dispb_sd_d rw input data dispb_sd_d d7 d6 d5 d4 d3 d2 d1 d0 (output) (input) write read dispb_ser_rs dispb_ser_rs 1 display if clock cycle 1 display if clock cycle 1 display if clock cycle 1 display if clock cycle 1 display if clock cycle 1 display if clock cycle
mcimx31/mcimx31l technical data, rev. 4.1 82 freescale semiconductor electrical characteristics 4.3.15.5.4 serial interfaces, electrical characteristics figure 65 depicts timing of the serial interface. table 51 lists the timing parameters at display access level. figure 65. asynchronous serial interface timing diagram table 51. asynchronous serial interface timing parameters?access level id parameter symbol min. typ. 1 max. units ip48 read system cycle time tcycr tdicpr?1.5 tdicpr 2 tdicpr+1.5 ns ip49 write system cycle time tcycw tdicpw?1.5 tdicpw 3 tdicpw+1.5 ns ip50 read clock low pulse width trl tdicdr?tdicur?1.5 tdicdr 4 ?tdicur 5 tdicdr?tdicur+1.5 ns ip51 read clock high pulse width trh tdicpr?tdicdr+tdicur?1.5 tdicpr?tdicdr+ tdicur tdicpr?tdicdr+tdicur+1.5 ns ip52 write clock low pulse width twl tdicdw?tdicuw?1.5 tdicdw 6 ?tdicuw 7 tdicdw?tdicuw+1.5 ns ip53 write clock high pulse width twh tdicpw?tdicdw+ tdicuw?1.5 tdicpw?tdicdw+ tdicuw tdicpw?tdicdw+ tdicuw+1.5 ns ip54 controls setup time for read tdcsr tdicur?1.5 tdicur ? ns ip55 controls hold time for read tdchr tdicpr?tdicdr?1.5 tdicpr?tdicdr ? ns ip49, ip48 read data ip51, ip53 ip58 ip59 dispb_ser_rs dispb_data dispb_data (input) (output) ip56,ip54 ip57, ip55 ip50, ip52 ip61 ip60 ip67,ip65 ip47 ip64, ip66 ip62, ip63 dispb_sd_d_clk read point
electrical characteristics mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 83 ip56 controls setup time for write tdcsw tdicuw?1.5 tdicuw ? ns ip57 controls hold time for write tdchw tdicpw?tdicdw?1.5 tdicpw?tdicdw ? ns ip58 slave device data delay 8 tracc 0 ? tdrp 9 ?tlbd 10 ?tdicur?1.5 ns ip59 slave device data hold time 8 troh tdrp?tlbd?tdicdr+1.5 ? tdicpr?tdicdr?1.5 ns ip60 write data setup time tds tdicdw?1.5 tdicdw ? ns ip61 write data hold time tdh tdicpw?tdicdw?1.5 tdicpw?tdicdw ? ns ip62 read period 2 tdicpr tdicpr?1.5 tdicpr tdicpr+1.5 ns ip63 write period 3 tdicpw tdicpw?1.5 tdicpw tdicpw+1.5 ns ip64 read down time 4 tdicdr tdicdr?1.5 tdicdr tdicdr+1.5 ns ip65 read up time 5 tdicur tdicur?1.5 tdicur tdicur+1.5 ns ip66 write down time 6 tdicdw tdicdw?1.5 tdicdw tdicdw+1.5 ns ip67 write up time 7 tdicuw tdicuw?1.5 tdicuw tdicuw+1.5 ns ip68 read time point 9 tdrp tdrp?1.5 tdrp tdrp+1.5 ns 1 the exact conditions have not been finalized, but will likely matc h the current customer requirement for their specific display . these conditions may be device specific. 2 display interface clock period value for read: 3 display interface clock period value for write: 4 display interface clock down time for read: 5 display interface clock up time for read: 6 display interface clock down time for write: 7 display interface clock up time for write: 8 this parameter is a requirement to the display connected to the ipu. 9 data read point: 10 loopback delay tlbd is the cumulative propagation delay of read controls and read data. it includes an ipu output delay, a device-level output delay, board delays, a device-level input delay, an ipu input delay. this value is device specific. table 51. asynchronous serial interface timing parameters?access level (continued) id parameter symbol min. typ. 1 max. units tdicpr t hsp_clk ceil ? disp#_if_clk_per_rd hsp_clk_period ---------------------------------------------------------------- = tdicpw t hsp_clk ceil ? disp#_if_clk_per_wr hsp_clk_period ----------------------------------------------------------------- - = tdicdr 1 2 -- - t hsp_clk ceil 2 disp#_if_clk_down_rd ? hsp_clk_period ------------------------------------------------------------------------------- ? = tdicur 1 2 -- - t hsp_clk ceil 2 disp#_if_clk_up_rd ? hsp_clk_period -------------------------------------------------------------------- ? = tdicdw 1 2 -- - t hsp_clk ceil 2 disp#_if_clk_down_wr ? hsp_clk_period -------------------------------------------------------------------------------- - ? = tdicuw 1 2 -- - t hsp_clk ceil 2 disp#_if_clk_up_wr ? hsp_clk_period --------------------------------------------------------------------- - ? = tdrp t hsp_clk ceil disp#_read_en hsp_clk_period -------------------------------------------------- ? =
mcimx31/mcimx31l technical data, rev. 4.1 84 freescale semiconductor electrical characteristics the disp#_if_clk_per_wr, disp#_if_clk_per_rd, hsp_clk_period, disp#_if_clk_down_wr, disp#_if_clk_up_wr, disp#_if_clk_down_rd, disp#_if_clk_up_rd and disp#_read_en parameters are programmed via the di_disp#_time_conf_1, di_disp#_time_con f_2 and di_hsp_clk_per registers. 4.3.16 memory stick host controller (mshc) figure 66 , figure 67 , and figure 68 depict the mshc timings, and table 52 and table 53 list the timing parameters. figure 66. mshc_clk timing diagram figure 67. transfer operat ion timing diagram (serial) tsclkwh tsclkwl tsclkc tsclkr tsclkf mshc_sclk tsclkc mshc_sclk tbssu tbsh tdsu tdh mshc_bs mshc_data (output) tdd mshc_data (intput)
electrical characteristics mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 85 figure 68. transfer operati on timing diagram (parallel) note the memory stick host controller is designed to meet the timing requirements per sony's memory stick pro format specifications document. tables in this section deta ils the specifications requi rements for parallel and serial modes, and not the mcimx31 timing. table 52. serial interf ace timing parameters 1 1 timing is guaranteed for nvcc from 2.7 through 3.1 v and up to a maximum overdrive nvcc of 3.3 v. see nvcc restrictions described in table 8, "operating ranges," on page 13 . signal parameter symbol standards unit min. max. mshc_sclk cycle tsclkc 50 ? ns h pulse length tsclkwh 15 ? ns l pulse length tsclkwl 15 ? ns rise time tsclkr ? 10 ns fall time tsclkf ? 10 ns mshc_bs setup time tbssu 5 ? ns hold time tbsh 5 ? ns mshc_data setup time tdsu 5 ? ns hold time tdh 5 ? ns output delay time tdd ? 15 ns tsclkc mshc_sclk tbssu tbsh tdsu tdh mshc_bs mshc_data (output) tdd mshc_data (intput)
mcimx31/mcimx31l technical data, rev. 4.1 86 freescale semiconductor electrical characteristics 4.3.17 personal computer memory card international association (pcmcia) figure 69 and figure 70 depict the timings pertaining to the pcmcia module, each of which is an example of one clock of strobe set-up ti me and one clock of strobe hold time. table 54 lists the timing parameters. table 53. parallel interface timing parameters 1 1 timing is guaranteed for nvcc from 2.7 through 3.1 v and up to a maximum overdrive nvcc of 3.3 v. see nvcc restrictions described in table 8, "operating ranges," on page 13 . signal parameter symbol standards unit min max mshc_sclk cycle tsclkc 25 ? ns h pulse length tsclkwh 5 ? ns l pulse length tsclkwl 5 ? ns rise time tsclkr ? 10 ns fall time tsclkf ? 10 ns mshc_bs setup time tbssu 8 ? ns hold time tbsh 1 ? ns mshc_data setup time tdsu 8 ? ns hold time tdh 1 ? ns output delay time tdd ? 15 ns
electrical characteristics mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 87 figure 69. write accesses timing diagram?psht=1, psst=1 hclk haddr addr 1 control control 1 hwdata data write 1 hready hresp okay okay okay a[25:0] addr 1 d[15:0] data write 1 wait reg reg oe/we/iord/iowr ce1/ce2 rw poe psst psht psl
mcimx31/mcimx31l technical data, rev. 4.1 88 freescale semiconductor electrical characteristics figure 70. read a ccesses timing diagram?psht=1, psst=1 4.3.18 pwm electrical specifications this section describes the electrical information of the pwm. the pwm can be programmed to select one of three clock signals as its source frequency. the sel ected clock signal is passed through a prescaler before being input to the counter. the output is available at the pulse-width modulator output (pwmo) external pin. table 54. pcmcia write and read timing parameters symbol parameter min max unit psht pcmcia strobe hold time 0 63 clock psst pcmcia strobe set up time 1 63 clock psl pcmcia strobe length 1 128 clock hclk haddr addr 1 control control 1 rwdata data read 1 hready hresp okay okay okay a[25:0] addr 1 d[15:0] wait reg reg oe/we/iord/iowr ce1/ce2 rw poe psst psht psl
electrical characteristics mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 89 4.3.18.1 pwm timing figure 71 depicts the timing of the pwm, and table 55 lists the pwm ti ming characteristics. figure 71. pwm timing 4.3.19 sdhc electrical specifications this section describes the electr ical information of the sdhc. 4.3.19.1 sdhc timing figure 72 depicts the timings of the sdhc, and table 56 lists the timing parameters. table 55. pwm output timing parameters id parameter min max unit 1 system clk frequency 1 1 cl of pwmo = 30 pf 0 ipg_clk mhz 2a clock high time 12.29 ? ns 2b clock low time 9.91 ? ns 3a clock fall time ? 0.5 ns 3b clock rise time ? 0.5 ns 4a output delay time ? 9.37 ns 4b output setup time 8.71 ? ns 4a system clock 2a 1 pwm output 2b 3a 3b 4b
mcimx31/mcimx31l technical data, rev. 4.1 90 freescale semiconductor electrical characteristics figure 72. sdhc timing diagram 4.3.20 sim electrical specifications each sim card interface consist of a total of 12 pins (for 2 separate ports of 6 pi ns each. mostly one port with 5 pins is used). table 56. sdhc interface timing parameters id parameter symbol min max unit card input clock sd1 clock frequency (low speed) f pp 1 1 in low speed mode, card clock must be lower than 400 khz, voltage r anges from 2.7 v?3.3 v. 0 400 khz clock frequency (sd/sdio full speed) f pp 2 2 in normal data transfer mode for sd/sdio card, clock frequency can be any value between 0 mhz?25 mhz. 025mhz clock frequency (mmc full speed) f pp 3 3 in normal data transfer mode for mmc card, clock frequency can be any value between 0 mhz?20 mhz. 020mhz clock frequency (identification mode) f od 4 4 in card identification mode, card clock must be 100 khz?400 khz, voltage ranges from 2.7 v?3.3 v. 100 400 khz sd2 clock low time t wl 10 ? ns sd3 clock high time t wh 10 ? ns sd4 clock rise time t tlh ?10ns sd5 clock fall time t thl ?10ns sdhc output/card inputs cmd, dat (reference to clk) sd6 sdhc output delay t odl ?6.5 3 ns sdhc input/card outputs cmd, dat (reference to clk) sd7 sdhc input setup t is ?18.5ns sd8 sdhc input hold t ih ? ?11.5 ns sd1 sd5 sd7 sd4 sd8 cmd output from sdhc to card data[3:0] input to sdhc clk sd2 sd6 sd3 cmd data[3:0]
electrical characteristics mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 91 the interface is meant to be used with synchronous sim cards. this means that the sim module provides a clock for the sim card to use. the frequency of th is clock is normally 372 ti mes the data rate on the tx/rx pins, however sim module can work with clk equal to 16 times the data rate on tx/rx pins. there is no timing relationship between the clock a nd the data. the clock that the sim module provides to the aim card will be used by th e sim card to recover the clock from th e data much like a standard uart. all six (or 5 in case bi-directiona l txrx is used) of the pins fo r each half of the sim module are asynchronous to each other. there are no required timing relationshi ps between the signals in normal mode, but there are some in two specific cases: reset and power down sequences. 4.3.20.1 general timing requirements figure 73 shows the timing of the sim module, and figure 57 lists the timing parameters. figure 73. sim clock timing diagram 4.3.20.2 reset sequence 4.3.20.2.1 cards with internal reset the sequence of reset for this kind of sim cards is as follows (see figure 74 ): ? after powerup, the clock signal is enabled on sgclk (time t0) ? after 200 clock cycl es, rx must be high. ? the card must send a response on rx acknowledging the reset be tween 400 and 40000 clock cycles after t0. table 57. sim timing specification?high drive strength num description symbol min max unit 1 sim clock frequency (clk) 1 1 50% duty cycle clock s freq 0.01 5 (some new cards may reach 10) mhz 2 sim clk rise time 2 2 with c = 50pf s rise ?20ns 3 sim clk fall time 3 3 with c = 50pf s fall ?20ns 4 sim input transition time (rx, simpd) s trans ?25ns clk srise sfall 1/sfreq
mcimx31/mcimx31l technical data, rev. 4.1 92 freescale semiconductor electrical characteristics figure 74. internal-reset card reset sequence 4.3.20.2.2 cards with active low reset the sequence of reset for this kind of card is as follows (see figure 75 ): 1. after powerup, the clock signal is enabled on clk (time t0) 2. after 200 clock cycl es, rx must be high. 3. rst must remain low for at least 40000 clock cycl es after t0 (no response is to be received on rx during those 40000 clock cycles) 4. rst is set high (time t1) 5. rst must remain high for at least 40000 clock cy cles after t1 and a res ponse must be received on rx between 400 and 40000 clock cycles after t1. figure 75. active-low-reset card reset sequence sven clk rx 2 t0 1 response 2 1 < 200 clock cycles < 40000 clock cycles 400 clock cycles < sven clk rx 2 t0 1 response rst t1 1 2 < 200 clock cycles < 40000 clock cycles 400 clock cycles < 3 3 3 400000 clock cycles <
electrical characteristics mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 93 4.3.20.3 power down sequence power down sequence for sim interface is as follows: 1. simpd port detects the removal of the sim card 2. rst goes low 3. clk goes low 4. tx goes low 5. ven goes low each of this steps is done in one ckil period (usua lly 32 khz). power down can be started because of a sim card removal detection or launched by the processor. figure 76 and table 58 show the usual timing requirements for this sequence, wi th fckil = ckil frequency value. figure 76. smartcard interface power down ac timing table 58. timing requirements for power down sequence num description symbol min max unit 1 sim reset to sim clock stop s rst2clk 0.9*1/fckil 0.8 s 2 sim reset to sim tx data low s rst2dat 1.8*1/fckil 1.2 s 3 sim reset to sim voltage enable low s rst2ven 2.7*1/fckil 1.8 s 4 sim presence detect to sim reset low s pd2rst 0.9*1/fckil 25 ns simpd rst clk data_tx sven srst2clk srst2dat srst2ven spd2rst
mcimx31/mcimx31l technical data, rev. 4.1 94 freescale semiconductor electrical characteristics 4.3.21 sjc electrical specifications this section details the electrical characteristics for the sjc module. figure 77 depicts the sjc test clock input timing. figure 78 depicts the sjc boundary scan timing, figure 79 depicts the sjc test access port, figure 80 depicts the sjc trst timing, and table 59 lists the sjc timing parameters. figure 77. test clock input timing diagram figure 78. boundary scan (jtag) timing diagram tck (input) vm vm vih vil sj1 sj2 sj2 sj3 sj3 tck (input) data inputs data outputs data outputs data outputs vih vil input data valid output data valid output data valid sj4 sj5 sj6 sj7 sj6
electrical characteristics mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 95 figure 79. test access port timing diagram figure 80. trst timing diagram table 59. sjc timing parameters id parameter all frequencies unit min max sj1 tck cycle time 100 1 ?ns sj2 tck clock pulse width measured at v m 2 40 ? ns sj3 tck rise and fall times ? 3 ns sj4 boundary scan input data set-up time 10 ? ns sj5 boundary scan input data hold time 50 ? ns sj6 tck low to output data valid ? 50 ns sj7 tck low to output high impedance ? 50 ns sj8 tms, tdi data set-up time 10 ? ns sj9 tms, tdi data hold time 50 ? ns sj10 tck low to tdo data valid ? 44 ns tck (input) tdi (input) tdo (output) tdo (output) tdo (output) vih vil input data valid output data valid output data valid tms sj8 sj9 sj10 sj11 sj10 tck (input) trst (input) sj13 sj12
mcimx31/mcimx31l technical data, rev. 4.1 96 freescale semiconductor electrical characteristics 4.3.22 ssi electrical specifications this section describes the electri cal information of ssi. note th e following pertaining to timing information: ? all the timings for the ssi are given for a non-inverted serial cloc k polarity (tsc kp/rsckp = 0) and a non-inverted frame sync (tfsi/rfsi = 0). if th e polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal stck/srck and/or the frame sync stfs/srfs shown in the tables and in the figures. ? all timings are on audmux signals when ssi is being used for data transfer. ? ?tx? and ?rx? refer to the transm it and receive sections of the ssi. ? for internal frame sync operation using external clock, the fs ti ming will be same as that of tx data (for example, during ac97 mode of operation). 4.3.22.1 ssi transmitter timing with internal clock figure 81 depicts the ssi tran smitter timing with internal clock, and table 60 lists the timing parameters. sj11 tck low to tdo high impedance ? 44 ns sj12 trst assert time 100 ? ns sj13 trst set-up time to tck low 40 ? ns 1 on cases where sdma tap is put in the chain, the max tck fre quency is limited by max ratio of 1:8 of sdma core frequency to tck limitation. this implies max frequency of 8.25 mhz (or 121.2 ns) for 66 mhz ipg clock. 2 v m - mid point voltage table 59. sjc timing parameters (continued) id parameter all frequencies unit min max
electrical characteristics mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 97 figure 81. ssi transmitter with internal clock timing diagram ss19 ad1_txc ad1_txfs (bl) ad1_txfs (wl) ss1 ad1_txd ad1_rxd ss2 ss4 ss3 ss5 ss6 ss8 ss10 ss12 ss14 ss18 ss15 ss17 ss16 ss43 ss42 note: srxd input in synchronous mode only (output) (output) (output) (output) (input) ss19 dam1_t_clk dam1_t_fs (bl) dam1_t_fs (wl) ss1 dam1_txd dam1_rxd ss2 ss4 ss3 ss5 ss6 ss8 ss10 ss12 ss14 ss18 ss15 ss17 ss16 ss42 note: srxd input in synchronous mode only (output) (output) (output) (output) (input) ss43
mcimx31/mcimx31l technical data, rev. 4.1 98 freescale semiconductor electrical characteristics table 60. ssi transmitter with in ternal clock timing parameters id parameter min max unit internal clock operation ss1 (tx/rx) ck clock period 81.4 ? ns ss2 (tx/rx) ck clock high period 36.0 ? ns ss3 (tx/rx) ck clock rise time ? 6 ns ss4 (tx/rx) ck clock low period 36.0 ? ns ss5 (tx/rx) ck clock fall time ? 6 ns ss6 (tx) ck high to fs (bl) high ? 15.0 ns ss8 (tx) ck high to fs (bl) low ? 15.0 ns ss10 (tx) ck high to fs (wl) high ? 15.0 ns ss12 (tx) ck high to fs (wl) low ? 15.0 ns ss14 (tx/rx) internal fs rise time ? 6 ns ss15 (tx/rx) internal fs fall time ? 6 ns ss16 (tx) ck high to stxd valid from high impedance ? 15.0 ns ss17 (tx) ck high to stxd high/low ? 15.0 ns ss18 (tx) ck high to stxd high impedance ? 15.0 ns ss19 stxd rise/fall time ? 6 ns synchronous internal clock operation ss42 srxd setup before (tx) ck falling 10.0 ? ns ss43 srxd hold after (tx) ck falling 0 ? ns ss52 loading ? 25 pf
electrical characteristics mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 99 4.3.22.2 ssi receiver timing with internal clock figure 82 depicts the ssi receiver timing with internal clock, and table 61 lists the timing parameters. figure 82. ssi receiver with internal clock timing diagram ss50 ss48 ad1_txc ad1_txfs (bl) ad1_txfs (wl) ad1_rxd ad1_rxc ss1 ss4 ss2 ss51 ss20 ss21 ss49 ss7 ss9 ss11 ss13 ss47 (output) (output) (output) (input) (output) ss3 ss5 ss50 ss48 dam1_t_clk dam1_t_fs (bl) dam1_t_fs (wl) dam1_rxd dam1_r_clk ss3 ss1 ss4 ss2 ss5 ss51 ss20 ss21 ss49 ss7 ss9 ss11 ss13 ss47 (output) (output) (output) (input) (output)
mcimx31/mcimx31l technical data, rev. 4.1 100 freescale semiconductor electrical characteristics table 61. ssi receiver with internal clock timing parameters id parameter min max unit internal clock operation ss1 (tx/rx) ck clock period 81.4 ? ns ss2 (tx/rx) ck clock high period 36.0 ? ns ss3 (tx/rx) ck clock rise time ? 6 ns ss4 (tx/rx) ck clock low period 36.0 ? ns ss5 (tx/rx) ck clock fall time ? 6 ns ss7 (rx) ck high to fs (bl) high ? 15.0 ns ss9 (rx) ck high to fs (bl) low ? 15.0 ns ss11 (rx) ck high to fs (wl) high ? 15.0 ns ss13 (rx) ck high to fs (wl) low ? 15.0 ns ss20 srxd setup time before (rx) ck low 10.0 ? ns ss21 srxd hold time after (rx) ck low 0 ? ns oversampling clock operation ss47 oversampling clock period 15.04 ? ns ss48 oversampling clock high period 6 ? ns ss49 oversampling clock rise time ? 3 ns ss50 oversampling clock low period 6 ? ns ss51 oversampling clock fall time ? 3 ns
electrical characteristics mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 101 4.3.22.3 ssi transmitter ti ming with external clock figure 83 depicts the ssi transmitter t iming with external clock, and table 62 lists the timing parameters. figure 83. ssi transmitter with external clock timing diagram ss45 ss33 ss24 ss26 ss25 ss23 ad1_txc ad1_txfs (bl) ad1_txfs (wl) ad1_txd ad1_rxd note: srxd input in synchronous mode only ss31 ss29 ss27 ss22 ss44 ss39 ss38 ss37 ss46 (input) (input) (input) (output) (input) ss45 ss33 ss24 ss26 ss25 ss23 dam1_t_clk dam1_t_fs (bl) dam1_t_fs (wl) dam1_txd dam1_rxd note: srxd input in synchronous mode only ss31 ss29 ss27 ss22 ss44 ss39 ss38 ss37 ss46 (input) (input) (input) (output) (input)
mcimx31/mcimx31l technical data, rev. 4.1 102 freescale semiconductor electrical characteristics table 62. ssi transmitter with external clock timing parameters id parameter min max unit external clock operation ss22 (tx/rx) ck clock period 81.4 ? ns ss23 (tx/rx) ck clock high period 36.0 ? ns ss24 (tx/rx) ck clock rise time ? 6.0 ns ss25 (tx/rx) ck clock low period 36.0 ? ns ss26 (tx/rx) ck clock fall time ? 6.0 ns ss27 (tx) ck high to fs (bl) high ?10.0 15.0 ns ss29 (tx) ck high to fs (bl) low 10.0 ? ns ss31 (tx) ck high to fs (wl) high ?10.0 15.0 ns ss33 (tx) ck high to fs (wl) low 10.0 ? ns ss37 (tx) ck high to stxd valid from high impedance ? 15.0 ns ss38 (tx) ck high to stxd high/low ? 15.0 ns ss39 (tx) ck high to stxd high impedance ? 15.0 ns synchronous external clock operation ss44 srxd setup before (tx) ck falling 10.0 ? ns ss45 srxd hold after (tx) ck falling 2.0 ? ns ss46 srxd rise/fall time ? 6.0 ns
electrical characteristics mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 103 4.3.22.4 ssi receiver ti ming with external clock figure 84 depicts the ssi receiver timing with external clock, and table 63 lists the timing parameters. figure 84. ssi receiver with external clock timing diagram table 63. ssi receiver with external clock timing parameters id parameter min max unit external clock operation ss22 (tx/rx) ck clock period 81.4 ? ns ss23 (tx/rx) ck clock high period 36.0 ? ns ss24 (tx/rx) ck clock rise time ? 6.0 ns ss25 (tx/rx) ck clock low period 36.0 ? ns ss26 (tx/rx) ck clock fall time ? 6.0 ns ss24 ss34 ss35 ss30 ss28 ss26 ss25 ss23 ad1_txc ad1_txfs (bl) ad1_txfs (wl) ad1_rxd ss40 ss22 ss32 ss36 ss41 (input) (input) (input) (input) ss24 ss34 ss35 ss30 ss28 ss26 ss25 ss23 dam1_t_clk dam1_t_fs (bl) dam1_t_fs (wl) dam1_rxd ss40 ss22 ss32 ss36 ss41 (input) (input) (input) (input)
mcimx31/mcimx31l technical data, rev. 4.1 104 freescale semiconductor electrical characteristics 4.3.23 usb electrical specifications this section describes the electrical information of the usbotg port. the otg port supports both serial and parallel interfaces. the high speed (hs) interface is supported vi a the ulpi (ultra low pin count interface). figure 85 depicts the usb ulpi timing diagram, and table 64 lists the timing parameters. figure 85. usb ulpi interface timing diagram ss28 (rx) ck high to fs (bl) high ?10.0 15.0 ns ss30 (rx) ck high to fs (bl) low 10.0 ? ns ss32 (rx) ck high to fs (wl) high ?10.0 15.0 ns ss34 (rx) ck high to fs (wl) low 10.0 ? ns ss35 (tx/rx) external fs rise time ? 6.0 ns ss36 (tx/rx) external fs fall time ? 6.0 ns ss40 srxd setup time before (rx) ck low 10.0 ? ns ss41 srxd hold time after (rx) ck low 2.0 ? ns table 64. usb ulpi interface timing specification 1 1 timing parameters are given as viewed by transceiver side. parameter symbol min max units setup time (control in, 8-bit data in) t sc , t sd 6? ns hold time (control in, 8-bit data in) t hc , t hd 0 ? ns output delay (control out, 8-bit data out) t dc , t dd ?9 ns table 63. ssi receiver with external clock timing parameters (continued) id parameter min max unit clock control out (stp) data out control in (dir, nxt) data in t dd t dc t dc t sc t sd t hd t hc
package informat ion and pinout mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 105 5 package information and pinout this section includes the contact assignment inform ation and mechanical package drawing for the mcimx31. 5.1 mapbga production package?457 14 x 14 mm, 0.5 mm pitch this section contains the outline dr awing, signal assignment map (see section 8, ?revision history ,? table 70 for the 0.5 mm 14 14 mapbga signal assignments), and mapbga ground/power id by ball grid location for the 457 14 x 14 mm, 0.5 mm pitch package. 5.1.1 production package outline drawing? 14 x 14 mm 0.5 mm figure 86. production package: case 1581?0.5 mm pitch
mcimx31/mcimx31l technical data, rev. 4.1 106 freescale semiconductor package information and pinout 5.1.2 mapbga signal assignment?14 14 mm 0.5 mm see section 8, ?revision history ,? figure 70 for the 0.5 mm 14 14 mapbga signal assignments. 5.1.3 connection tables? 14 x 14 mm 0.5 mm table 65 shows the device connection list for power and ground, alpha-sorted. table 66 shows the device connection list for signals. 5.1.3.1 ground and power id locations? 14 x 14 mm 0.5 mm table 65. 14 x 14 mapbga ground/power id by ball grid location gnd/pwr id ball location fgnd ab24 fuse_vdd ac24 fvcc aa24 gnd a1, a2, a25, a26, b1, b2, b25, b26, c1, c2, c24, c25, c26, d1, d25, e22, e24, f21, l12, m 11, m12, m13, m14, m15, m16, n12, n13, n14, n 15, n16, p12, p13, p14, p15, p16, r12, r13, r14, r15, r16, t12, t13, v17, ac2, ac26, ad1, ad2, ad24, ad25, ad26, ae1, ae2 , ae24, ae25, ae26, af 1, af2, af25, af26 ioqvdd y6 mgnd t15 mvcc v15 nvcc1 g19, g21, k18 nvcc2 y17, y18, y19, y20 nvcc3 l9, m9, n11 nvcc4 l18, l19 nvcc5 e5, f6, g7 nvcc6 j15, j16, k15 nvcc7 n18, p18, r18, t18 nvcc8 j12, j13 nvcc9 j17 nvcc10 p9, p11, r11, t11 nvcc21 y14, y15, y16 nvcc22 w7, y7, y8, y9, y10, y11, y12, y13, aa6 qvcc j14, l13, l14, l15, l16, m 18, u18, v10, v11, v12, v13 qvcc1 j10, j11, k9, l11 qvcc4 n9, r9, t9, u9 sgnd t14 svcc v14 uvcc v16 ugnd t16
package informat ion and pinout mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 107 5.1.3.2 bga signal id by ball grid location?14 x 14 0.5 mm table 66 shows the device connection list for signals only, alpha-sorted by signal identification. table 66. 14 x 14 bga signal id by ball grid location signal id ball location signal id ball location a0 ad6 ckil h21 a1 af5 clko c23 a10 af18 clkss g26 a11 ac3 compare g18 a12 ad3 contrast r24 a13 ad4 cs0 ae23 a14 af17 cs1 af23 a15 af16 cs2 ae21 a16 af15 cs3 ad22 a17 af14 cs4 af24 a18 af13 cs5 af22 a19 af12 csi_d10 m24 a2 ab5 csi_d11 l26 a20 af11 csi_d12 m21 a21 af10 csi_d13 m25 a22 af9 csi_d14 m20 a23 af8 csi_d15 m26 a24 af7 csi_d4 l21 a25 af6 csi_d5 k25 a3 ae4 csi_d6 l24 a4 aa3 csi_d7 k26 a5 af4 csi_d8 l20 a6 ab3 csi_d9 l25 a7 ae3 csi_hsync k20 a8 ad5 csi_mclk k24 a9 af3 csi_pixclk j26 ata_cs0 j6 csi_vsync j25 ata_cs1 f2 cspi1_miso p7 ata_dior e2 cspi1_mosi p2 ata_diow h6 cspi1_sclk n2 ata_dmack f1 cspi1_spi_rdy n3 ata _ r e s e t h3 cspi1_ss0 p3 batt_line f7 cspi1_ss1 p1 bclk ab26 cspi1_ss2 p6 boot_mode0 f20 cspi2_miso a4 boot_mode1 c21 cspi2_mosi e3 boot_mode2 d24 cspi2_sclk c7 boot_mode3 c22 cspi2_spi_rdy b6 boot_mode4 d26 cspi2_ss0 b5 capture a22 cspi2_ss1 c6 cas ad20 cspi2_ss2 a5 ce_control a14 cspi3_miso g3 ckih f24 cspi3_mosi d2
mcimx31/mcimx31l technical data, rev. 4.1 108 freescale semiconductor package information and pinout cspi3_sclk e1 gpio1_3 f25 cspi3_spi_rdy g6 gpio1_4 f19 cts1 b11 gpio1_5 (pwr rdy) b24 cts2 g13 gpio1_6 a23 d0 ab2 gpio3_0 k21 d1 y3 gpio3_1 h26 d10 y1 hsync n25 d11 u7 i2c_clk j24 d12 w2 i2c_dat h25 d13 v3 iois16 j3 d14 w1 key_col0 c15 d15 u6 key_col1 b17 d2 ab1 key_col2 g15 d3 w6 key_col3 a17 d3_cls r20 key_col4 c16 d3_rev t26 key_col5 b18 d3_spl u25 key_col6 f15 d4 aa2 key_col7 a18 d5 v7 key_row0 f13 d6 aa1 key_row1 b15 d7 w3 key_row2 c14 d8 y2 key_row3 a15 d9 v6 key_row4 g14 dcd_dce1 b12 key_row5 b16 dcd_dte1 b13 key_row6 f14 de c18 key_row7 a16 dqm0 ae19 l2pg see vpg1 dqm1 ad19 lba ae22 dqm2 aa20 lcs0 p26 dqm3 ae18 lcs1 p21 drdy0 n26 ld0 t24 dsr_dce1 a11 ld1 u26 dsr_dte1 a12 ld10 v24 dtr_dce1 c11 ld11 y25 dtr_dce2 f12 ld12 y26 dtr_dte1 c12 ld13 v21 dvfs0 e25 ld14 aa25 dvfs1 g24 ld15 w24 eb0 w21 ld16 aa26 eb1 y24 ld17 v20 ecb ad23 ld2 t21 fpshift n21 ld3 v25 gpio1_0 f18 ld4 t20 gpio1_1 b23 ld5 v26 gpio1_2 c20 ld6 u24 ld7 w25 sck6 t2 table 66. 14 x 14 bga signal id by ball grid location (continued) signal id ball location signal id ball location
package informat ion and pinout mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 109 ld8 u21 sclk0 b22 ld9 w26 sd_d_clk p24 m_grant y21 sd_d_i n20 m_request ac25 sd_d_io p25 ma10 ac1 sd0 ad18 mcupg see vpg0 sd1 ae17 nfale v1 sd1_clk m7 nfce t6 sd1_cmd l2 nfcle u3 sd1_data0 m6 nfrb u1 sd1_data1 l1 nfre v2 sd1_data2 l3 nfwe t7 sd1_data3 k2 nfwp u2 sd10 ae15 oe ab25 sd11 ae14 par_rs r21 sd12 ad14 pc_bvd1 h2 sd13 aa14 pc_bvd2 k6 sd14 ae13 pc_cd1 l7 sd15 ad13 pc_cd2 k1 sd16 aa13 pc_poe j7 sd17 ad12 pc_pwron k3 sd18 aa12 pc_ready j2 sd19 ae11 pc_rst h1 sd2 aa19 pc_rw g2 sd20 ae10 pc_vs1 j1 sd21 aa11 pc_vs2 k7 sd22 ae9 pc_wait l6 sd23 aa10 por h24 sd24 ae8 power_fail e26 sd25 ad10 pwmo g1 sd26 ae7 ras af19 sd27 aa9 read p20 sd28 aa8 reset_in j21 sd29 ad9 ri_dce1 f11 sd3 aa18 ri_dte1 g12 sd30 ae6 rtck c17 sd31 aa7 rts1 g11 sd4 ad17 rts2 b14 sd5 aa17 rw ab22 sd6 ae16 rxd1 a10 sd7 aa16 rxd2 a13 sd8 ad15 sck3 r2 sd9 aa15 sck4 c4 sdba0 ad7 sck5 d3 sdba1 ae5 sdcke0 ad21 trstb b20 sdcke1 af21 ttm_pad u20 table 66. 14 x 14 bga signal id by ball grid location (continued) signal id ball location signal id ball location
mcimx31/mcimx31l technical data, rev. 4.1 110 freescale semiconductor package information and pinout sdclk aa21 txd1 f10 sdclk ae20 txd2 c13 sdqs0 ad16 usb_byp a9 sdqs1 ae12 usb_oc c10 sdqs2 ad11 usb_pwr b10 sdqs3 ad8 usbh2_clk n1 sdwe af20 usbh2_data0 m1 ser_rs t25 usbh2_data1 m3 sfs3 r6 usbh2_dir n7 sfs4 f3 usbh2_nxt n6 sfs5 a3 usbh2_stp m2 sfs6 t3 usbotg_clk g10 simpd0 g17 usbotg_data0 f9 sjc_mod a20 usbotg_data1 b8 srst0 c19 usbotg_data2 g9 srx0 b21 usbotg_data3 a7 srxd3 r3 usbotg_data4 c8 srxd4 c3 usbotg_data5 b7 srxd5 b4 usbotg_data6 f8 srxd6 r7 usbotg_data7 a6 stx0 f17 usbotg_dir b9 stxd3 r1 usbotg_nxt a8 stxd4 b3 usbotg_stp c9 stxd5 c5 vpg0 g25 stxd6 t1 vpg1 j20 sven0 a21 vstby f26 tck b19 vsync0 n24 tdi f16 vsync3 r26 tdo a19 watchdog_rst a24 tms g16 write r25 table 66. 14 x 14 bga signal id by ball grid location (continued) signal id ball location signal id ball location
package informat ion and pinout mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 111 5.2 mapbga production package?473 19 x 19 mm, 0.8 mm pitch this section contains the outline dr awing, signal assignment map (see section 8, ?revision history ,? table 71 for the 19 x 19 mm, 0.8 mm pitch signal assign ments), and mapbga ground/power id by ball grid location for the 473 19 x 19 mm, 0.8 mm pitch package. 5.2.1 production package outline drawing?19 x 19 mm 0.8 mm figure 87. production package: case 1931?0.8 mm pitch
mcimx31/mcimx31l technical data, rev. 4.1 112 freescale semiconductor package information and pinout 5.2.2 mapbga signal assignment?19 19 mm 0.8 mm see table 71 for the 19 19 mm, 0.8 mm pitch signal assignments/ball map. 5.2.3 connection tables? 19 x 19 mm 0.8 mm table 67 shows the device connection list for power and ground, alpha-sorted followed by table 68 , which shows the no-connects. table 69 shows the device connection list for signals. 5.2.3.1 ground and power id locations? 19 x 19 mm 0.8 mm table 67. 19 x 19 bga ground/power id by ball grid location gnd/pwr id ball location fgnd u16 fuse_vdd t15 fvcc t16 gnd a1, a2, a3, a21, a22, a23, b1, b2, b 22, b23, c1, c2, c22, c23, d22, d23, j12, j13, k10, k11, k12, k13, k14, l10, l11, l12, l13, l14, m9, m10, m11, m12, m13, m14, n10, n11, n12, n13, n14, p10, p11, p12, p13, p14, r12, y1, y23, aa1, aa2, aa22, aa23, ab1, ab2, ab21, ab22, ab23, ac1, ac2, ac21, ac22, ac23 ioqvdd t8 mgnd u14 mvcc u15 nvcc1 g15, g16, h16, j17 nvcc2 n16, p16, r15, r16, t14 nvcc3 k7, k8, l7, l8 nvcc4 h14, j15, k15 nvcc5 g9, g10, h8, h9 nvcc6 g11, g12, g13, h12 nvcc7 h15, j16, k16, l16, m16 nvcc8 h10, h11, j11 nvcc9 g14 nvcc10 p8, r7, r8, r9, t9 nvcc21 t11, t12, t13, u11 nvcc22 t10, u7, u8, u9, u10, v6, v7, v8, v9, v10 qvcc h13, j14, l15, m15, n9, n15, p9, p15, r10, r11, r13, r14 qvcc1 j8, j9, j10, k9 qvcc4 l9, m7, m8, n8 sgnd u13 svcc u12 uvcc p18 ugnd p17
package informat ion and pinout mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 113 5.2.3.2 bga signal id by ba ll grid location?19 x 19 0.8 mm table 68. 19 x 19 bga no connects 1 1 these contacts are not used and must be floated by the user. signal ball location nc n7 nc p7 nc u21 table 69. 19 x 19 bga signal id by ball grid location signal id ball location signal id ball location a0 y6 ckil e21 a1 ac5 clko c20 a10 v15 clkss h17 a11 ab3 compare a20 a12 aa3 contrast n21 a13 y3 cs0 u17 a14 y15 cs1 y22 a15 y14 cs2 y18 a16 v14 cs3 y19 a17 y13 cs4 y20 a18 v13 cs5 aa21 a19 y12 csi_d10 k21 a2 ab5 csi_d11 k22 a20 v12 csi_d12 k23 a21 y11 csi_d13 l20 a22 v11 csi_d14 l18 a23 y10 csi_d15 l21 a24 y9 csi_d4 j20 a25 y8 csi_d5 j21 a3 aa5 csi_d6 l17 a4 y5 csi_d7 j22 a5 ac4 csi_d8 j23 a6 ab4 csi_d9 k20 a7 aa4 csi_hsync h22 a8 y4 csi_mclk h20 a9 ac3 csi_pixclk h23 ata_cs0 e1 csi_vsync h21 ata_cs1 g4 cspi1_miso n2 ata_dior e3 cspi1_mosi n1 ata_diow h6 cspi1_sclk m4 ata_dmack e2 cspi1_spi_rdy m1 ata _ r e s e t f3 cspi1_ss0 m2 batt_line f6 cspi1_ss1 n6 bclk w20 cspi1_ss2 m3 boot_mode0 f17 cspi2_miso b4 boot_mode1 c21 cspi2_mosi d5
mcimx31/mcimx31l technical data, rev. 4.1 114 freescale semiconductor package information and pinout boot_mode2 d20 cspi2_sclk b5 boot_mode3 f18 cspi2_spi_rdy d6 boot_mode4 e20 cspi2_ss0 c5 capture d18 cspi2_ss1 a4 cas aa20 cspi2_ss2 f7 ce_control d12 cspi3_miso d2 ckih f23 cspi3_mosi e4 cspi3_sclk h7 gpio1_3 g20 cspi3_spi_rdy f4 gpio1_4 d21 cts1 a9 gpio1_5 (pwr rdy) d19 cts2 c12 gpio1_6 g18 d0 u6 gpio3_0 g23 d1 w4 gpio3_1 k17 d10 v1 hsync l23 d11 u4 i2c_clk j18 d12 u3 i2c_dat k18 d13 r6 iois16 j7 d14 u2 key_col0 a15 d15 u1 key_col1 b15 d2 w3 key_col2 d14 d3 v4 key_col3 c15 d3_cls p20 key_col4 f13 d3_rev p21 key_col5 a16 d3_spl n17 key_col6 b16 d4 t7 key_col7 a17 d5 w2 key_row0 a13 d6 v3 key_row1 b13 d7 w1 key_row2 c13 d8 t6 key_row3 a14 d9 v2 key_row4 f12 dcd_dce1 c10 key_row5 d13 dcd_dte1 d11 key_row6 b14 de d16 key_row7 c14 dqm0 ab19 l2pg see vpg1 dqm1 y16 lba v17 dqm2 aa18 lcs0 m22 dqm3 ab18 lcs1 n23 drdy0 m17 ld0 r23 dsr_dce1 b10 ld1 r22 dsr_dte1 a11 ld10 u22 dtr_dce1 f10 ld11 r18 dtr_dce2 c11 ld12 u20 dtr_dte1 a10 ld13 v23 dvfs0 e22 ld14 v22 dvfs1 e23 ld15 v21 eb0 w22 ld16 v20 table 69. 19 x 19 bga signal id by ball grid location (continued) signal id ball location signal id ball location
package informat ion and pinout mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 115 eb1 w21 ld17 w23 ecb y21 ld2 r21 fpshift m23 ld3 r20 gpio1_0 c19 ld4 t23 gpio1_1 g17 ld5 t22 gpio1_2 b20 ld6 t21 ld7 t20 sck6 r2 ld8 r17 sclk0 b19 ld9 u23 sd_d_clk m21 m_grant u18 sd_d_i m20 m_request t17 sd_d_io m18 ma10 y2 sd0 ac18 mcupg see vpg0 sd1 aa17 nfale t2 sd1_clk k2 nfce r4 sd1_cmd k3 nfcle t1 sd1_data0 k4 nfrb r3 sd1_data1 j1 nfre t4 sd1_data2 j2 nfwe t3 sd1_data3 l6 nfwp p6 sd10 ab14 oe t18 sd11 ac14 par_rs p22 sd12 aa13 pc_bvd1 g2 sd13 ab13 pc_bvd2 h4 sd14 ac13 pc_cd1 j3 sd15 aa12 pc_cd2 h1 sd16 ac12 pc_poe j6 sd17 aa11 pc_pwron k6 sd18 ab11 pc_ready h2 sd19 ac11 pc_rst f1 sd2 ab17 pc_rw g3 sd20 aa10 pc_vs1 h3 sd21 ab10 pc_vs2 g1 sd22 ac10 pc_wait j4 sd23 ac9 por f21 sd24 aa9 power_fail f20 sd25 ac8 pwmo f2 sd26 ab8 ras aa19 sd27 ac7 read n18 sd28 aa8 reset_in f22 sd29 ab7 ri_dce1 d10 sd3 ac17 ri_dte1 b11 sd30 aa7 rtck d15 sd31 ac6 rts1 b9 sd4 aa16 rts2 b12 sd5 ac16 rw v18 sd6 aa15 table 69. 19 x 19 bga signal id by ball grid location (continued) signal id ball location signal id ball location
mcimx31/mcimx31l technical data, rev. 4.1 116 freescale semiconductor package information and pinout rxd1 c9 sd7 ab15 rxd2 a12 sd8 ac15 sck3 p1 sd9 aa14 sck4 g6 sdba0 aa6 sck5 d4 sdba1 y7 sdcke0 y17 trstb f15 sdcke1 v16 txd1 d9 sdclk ac20 txd2 f11 sdclk ac19 usb_byp c8 sdqs0 ab16 usb_oc b8 sdqs1 ab12 usb_pwr a8 sdqs2 ab9 usbh2_clk l1 sdqs3 ab6 usbh2_data0 m6 sdwe ab20 usbh2_data1 k1 ser_rs p23 usbh2_dir l2 sfs3 p2 usbh2_nxt l4 sfs4 d3 usbh2_stp l3 sfs5 g7 usbotg_clk d8 sfs6 p4 usbotg_data0 g8 simpd0 b18 usbotg_data1 c7 sjc_mod c17 usbotg_data2 a6 srst0 c18 usbotg_data3 f8 srx0 a19 usbotg_data4 d7 srxd3 n3 usbotg_data5 b6 srxd4 c3 usbotg_data6 a5 srxd5 c4 usbotg_data7 c6 srxd6 r1 usbotg_dir a7 stx0 f16 usbotg_nxt b7 stxd3 n4 usbotg_stp f9 stxd4 b3 vpg0 g21 stxd5 d1 vpg1 g22 stxd6 p3 vstby h18 sven0 d17 vsync0 l22 tck f14 vsync3 n20 tdi a18 watchdog_rst b21 tdo b17 write n22 tms c16 table 69. 19 x 19 bga signal id by ball grid location (continued) signal id ball location signal id ball location
mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 117 package information and pinout 5.3 ball maps table 70. ball map?14 x 14 0.5 mm pitch 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 a gnd gnd sfs5 cspi2 _miso cspi2_ ss2 usbot g_dat a7 usbot g_dat a3 usbot g_nxt usb_ byp rxd1 dsr_d ce1 dsr_d te1 rxd2 ce_co ntrol key_r ow3 key_r ow7 key_c ol3 key_c ol7 tdo sjc_m od sven0 captu re gpio1_ 6 watch dog_r st gnd gnd a b gnd gnd stxd4 srxd 5 cspi2_ ss0 cspi2_ spi_r dy usbot g_dat a5 usbot g_dat a1 usbot g_dir usb_p wr cts1 dcd_d ce1 dcd_d te1 rts2 key_r ow1 key_r ow5 key_c ol1 key_c ol5 tck trstb srx0 sclk0 gpio1_ 1 gpio1_ 5 gnd gnd b c gnd gnd srxd4 sck4 stxd5 cspi2_ ss1 cspi2_ sclk usbot g_dat a4 usbot g_stp usb_o c dtr_d ce1 dtr_d te1 txd2 key_r ow2 key_c ol0 key_c ol4 rtck de srst0 gpio1 _2 boot_ mode1 boot_ mode3 clko gnd gnd gnd c d gnd cspi3_ mosi sck5 boot_ mode2 gnd boot_ mode4 d e cspi3_ sclk ata _ d i or cspi2_ mosi nvcc5 gnd gnd dvfs0 power _fail e fata_d mack ata _ c s1 sfs4 nvcc5 batt_l ine usbot g_dat a6 usbot g_dat a0 txd1 ri_dc e1 dtr_d ce2 key_r ow0 key_r ow6 key_c ol6 tdi stx0 gpio1 _0 gpio1 _4 boot_ mode 0 gnd ckih gpio1_ 3 vstby f gpwmo pc_rw cspi3_ miso cspi3_ spi_r dy nvcc5 usbot g_dat a2 usbot g_clk rts1 ri_dt e1 cts2 key_r ow4 key_c ol2 tms simpd 0 comp are nvcc1 nvcc1 dvfs1 vpg0 clkss g hpc_rs t pc_bv d1 ata _ r eset ata _ d i ow ckil por i2c_da t gpio3_ 1 h jpc_vs 1 pc_re ady iois16 ata _ c s0 pc_po e qvcc1 qvcc1 nvcc8 nvcc8 qvcc nvcc6 nvcc6 nvcc9 vpg1 reset_ in i2c_cl k csi_vs ync csi_pix clk j kpc_cd 2 sd1_d ata 3 pc_pw ron pc_bv d2 pc_vs 2 qvcc1 nvcc6 nvcc1 csi_h sync gpio3_ 0 csi_mc lk csi_d5 csi_d7 k lsd1_d ata 1 sd1_c md sd1_d ata 2 pc_wa it pc_cd 1 nvcc3 qvcc1 gnd qvcc qvcc qv cc qvcc nvcc4 nvcc4 csi_d8 cs i_d4 csi_d6 csi_d9 csi_d1 1 l m usbh2 _data0 usbh2 _stp usbh2 _data1 sd1_d ata 0 sd1_c lk nvcc3 gnd gnd gnd gnd gnd gnd qvcc csi_d1 4 csi_d1 2 csi_d1 0 csi_d1 3 csi_d1 5 m n usbh2 _clk cspi1_ sclk cspi1_ spi_rd y usbh2 _nxt usbh2 _dir qvcc4 nvcc3 gnd gnd gnd gnd gnd nvcc7 sd_d_i fpshif t vsync 0 hsync drdy0 n p cspi1_ ss1 cspi1_ mosi cspi1_ ss0 cspi1_ ss2 cspi1_ miso nvcc1 0 nvcc1 0 gnd gnd gnd gnd gnd nvcc7 read lcs1 sd_d_ clk sd_d_i o lcs0 p r stxd3 sck3 srxd3 sfs3 srxd6 qvcc4 nvcc1 0 gnd gnd gnd gnd gnd nvcc7 d3_cl s par_rs contr ast write vsync 3 r t stxd6 sck6 sfs6 nfce nfwe qvcc4 nvcc1 0 gnd gnd sgnd mgnd ugnd nvcc7 ld4 ld2 ld0 ser_r s d3_rev t u nfrb nfwp nfcle d15 d11 qvcc4 qvcc ttm_p ad ld8 ld6 d3_spl ld1 u v nfale nfre d13 d9 d5 qvcc qvcc qvcc qvcc svcc mvcc uvcc gnd ld17 ld13 ld10 ld3 ld5 v w d14 d12 d7 d3 nvcc2 2 eb0 ld15 ld7 ld9 w y d10 d8 d1 ioqvd d nvcc2 2 nvcc2 2 nvcc2 2 nvcc2 2 nvcc2 2 nvcc2 2 nvcc2 2 nvcc2 1 nvcc2 1 nvcc2 1 nvcc2 nvcc2 nvcc2 nvcc2 m_gra nt eb1 ld11 ld12 y aa d6 d4 a4 nvcc2 2 sd31 sd28 sd27 sd23 sd21 sd18 sd16 sd13 sd9 sd7 sd5 sd3 sd2 dqm2 sdclk fvcc ld14 ld16 aa ab d2 d0 a6 a2 rw fgnd oe bclk ab ac ma10 gnd a11 fuse_v dd m_req uest gnd ac ad gnd gnd a12 a13 a8 a0 sdba0 sdqs3 sd29 sd25 sdqs2 sd17 sd15 sd12 sd8 sdqs0 sd4 sd0 dqm1 cas sdcke 0 cs3 ecb gnd gnd gnd ad ae gnd gnd a7 a3 sdba1 sd30 sd26 sd 24 sd22 sd20 sd19 sdqs1 sd14 sd11 sd10 sd6 sd1 dqm3 dqm0 sdclk cs2 lba cs0 gnd gnd gnd ae af gnd gnd a9 a5 a1 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a10 ras sdwe sdcke 1 cs5 cs1 cs4 gnd gnd af 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
mcimx31/mcimx31l technical data, rev. 4.1 118 freescale semiconductor package information and pinout table 71. ball map?19 x 19 0.8 mm pitch 1234 5 6 7 8 91011121314151617 181920212223 a gnd gnd gnd cspi2_ ss1 usbotg_ data6 usbotg _data2 usbotg _dir usb_ pwr cts1 dtr_ dte1 dsr_ dte1 rxd2 key_ row0 key_ row3 key_ col0 key_ col5 key_ col7 tdi srx0 compare gnd gnd gnd a b gnd gnd stxd4 cspi2_ miso cspi2_ sclk usbotg_ data5 usbotg_ nxt usb_ oc rts1 dsr_ dce1 ri_ dte1 rts2 key_ row1 key_ row6 key_ col1 key_ col6 tdo simpd0 sclk0 gpio1_2 watch dog_rst gnd gnd b c gnd gnd srxd4 srxd5 cspi2_ ss0 usbotg_ data7 usbotg_ data1 usb_ byp rxd1 dcd_ dce1 dtr_ dce2 cts2 key_ row2 key_ row7 key_ col3 tms sjc_ mod srst0 gpio1 _0 clko boot_ mode1 gnd gnd c d stxd5 cspi3_ miso sfs4 sck5 cspi2_ mosi cspi2_spi _rdy usbotg_ data4 usbotg_ clk txd1 ri_ dce1 dcd_ dte1 ce_ control key_ row5 key_ col2 rtck de sven0 capture gpio1 _5 boot_ mode2 gpio1_4 gnd gnd d e ata_ cs0 ata_ dmack ata_ dior cspi3_ mosi boot_ mode4 ckil dvfs0 dvfs1 e f pc_ rst pwmo ata_ reset cspi3_ spi_rdy batt_ line cspi2_ ss2 usbotg_ data3 usbot g_stp dtr_ dce1 txd2 key_ row4 key_ col4 tck trstb stx0 boot_ mode0 boot_ mode3 power_ fail por reset_ in ckih f g pc_vs2 pc_ bvd1 pc_ rw ata_ cs1 sck4 sfs5 usbotg_ data0 nvcc5 nvcc5 nvcc6 nvcc6 nvcc6 nvcc9 nvcc1 nv cc1 gpio1_1 gpio1_6 gpio1_3 vpg0 vpg1 gpio3_0 g h pc_cd2 pc_ ready pc_ vs1 pc_ bvd2 ata_ diow cspi3_ sclk nvcc5 nvcc5 nvcc8 nvcc8 nvcc6 qvcc nvcc4 nvcc7 nvcc1 clkss vstby csi_ mclk csi_ vsync csi_hsy nc csi_pix clk h j sd1_ data1 sd1_ data2 pc_ cd1 pc_ wait pc_poe iois16 qvcc1 qvcc1 qvcc1 nvcc8 gnd gnd qvcc nvcc4 nvcc7 nvcc1 i2c_ clk csi_d4 csi_d5 csi_d7 csi_d8 j k usbh2_ data1 sd1_ clk sd1_ cmd sd1_ data0 pc_ pwron nvcc3 nvcc3 qvcc1 gnd gnd gnd gnd gnd nvcc4 nvcc7 gpio3_1 i2c_ dat csi_d9 csi_ d10 csi_ d11 csi_ d12 k l usbh2_ clk usbh2_ dir usbh2_ stp usbh2_ nxt sd1_ data3 nvcc3 nvcc3 qvcc4 gnd gnd gnd gnd gnd qvcc nvcc7 csi_d6 csi_ d14 csi_d13 csi_d15 vsync0 hsync l m cspi1_s pi_rdy cspi1_ ss0 cspi1_ ss2 cspi1_ sclk usbh2_ data0 qvcc4 qvcc4 gnd gnd gnd gnd gnd gnd qvcc nvcc7 drdy0 sd_d_ io sd_d_i sd_d_ clk lcs0 fpshift m n cspi1_ mosi cspi1_ miso srxd3 stxd3 cspi1_ ss1 nc 1 1 these contacts are not used and must be floated by the user. qvcc4 qvcc gnd gnd gnd gnd gnd qvcc nvcc2 d3_ spl read vsync3 contrast write lcs1 n p sck3 sfs3 stxd6 sfs6 nfwp nc 1 nvcc10 qvcc gnd gnd gnd gnd gnd qvcc nvcc2 ugnd uvcc d3_cls d3_ rev par_ rs ser_ rs p r srxd6 sck6 nfrb nfce d13 nvcc10 nvcc10 nvcc1 0 qvcc qvcc gnd qvcc qvcc nvcc2 nvcc2 ld8 ld11 ld3 ld2 ld1 ld0 r t nfcle nfale nfwe nfre d8 d4 ioqvdd nvcc1 0 nvcc22 nvcc21 nvcc21 nvcc21 nvcc2 fuse_ vdd fvcc m_ request oe ld7 ld6 ld5 ld4 t u d15 d14 d12 d11 d0 nvcc22 nvcc22 nvcc2 2 nvcc22 nvcc21 svcc sgnd mgnd mvcc fgnd cs0 m_ grant ld12 nc ld10 ld9 u v d10 d9 d6 d3 nvcc22 nvcc22 nvcc22 nvcc2 2 nvcc22 a22 a20 a18 a16 a10 sdcke1 lba rw ld16 ld15 ld14 ld13 v w d7 d5 d2 d1 bclk eb1 eb0 ld17 w y gnd ma10 a13 a8 a4 a0 sdba1 a25 a24 a23 a21 a19 a17 a15 a14 dqm1 sdcke0 cs2 cs3 cs4 ecb cs1 gnd y aa gnd gnd a12 a7 a3 sdba0 sd30 sd28 sd24 sd20 sd17 sd15 sd12 sd9 sd6 sd4 sd1 dqm2 ras cas cs5 gnd gnd aa ab gnd gnd a11 a6 a2 sdqs3 sd29 sd26 sdqs2 sd21 sd18 sdqs1 sd13 sd10 sd7 sdqs0 sd2 dqm3 dqm0 sdwe gnd gnd gnd ab ac gnd gnd a9 a5 a1 sd31 sd27 sd25 sd23 sd22 sd19 sd16 sd14 sd11 sd8 sd5 sd3 sd0 sdclk sdclk gnd gnd gnd ac 1234 5 6 7 8 91011121314151617 181920212223
product differences mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 119 6 product differences the locations that provide the differences betwee n silicon revision 2.0, 1.2, and previous versions are given in table 72 . the differences between th e mcimx31/mcimx31l and the mcimx31c/mcimx31lc are outlined in table 73 . table 72. silicon differentiation by location within the data sheet item location silicon 1.2 and previous silicon 2.0 ordering information section 1.2, ?ordering information table 1 table 1 feature differences table 1.2.1, "feature differences between mask sets," on page 3 n/a table 1.2.1 operating ranges table 4.1, "chip-level conditions," on page 10 table 8, "operating ranges," on page 13 ta bl e 8 , and table 9, "specific operating ranges for silicon revision 2.0," on page 14 power-up sequences section 4.2.1, ?powering up figure 2, "power-up sequence for silicon revisions 1.2 and previous," on page 20 figure 3, "option 1 power-up sequence (silicon revision 2.0)," on page 21 power-down sequences section 4.2.2, ?powering down ?? table 73. product differentiation item location mcimx31/mcimx31l mcimx31c/mcimx31lc device ordering information table 1, "ordering information," on page 3 see ta bl e 1 .see ta bl e 1 . thermal simulation values table 6, "thermal resistance data?14 14 mm package," on page 11 and table 7, "thermal resistance data?19 19 mm package," on page 11 see ta bl e 6 and ta b l e 7 .see ta bl e 7 . core overdrive operating voltages table 8, "operating ranges," on page 13 capability to operate in overdrive voltages. not capable of overdrive operating voltages. fuse_vdd table 8, "operating ranges," on page 13 and table 9, "specific operating ranges for silicon revision 2.0," on page 14 fusebox read supply voltage 1.65 min, 1.95 max. in read mode, fuse_vdd should be floated. ambient operating temperature range table 13, "current consumption for ?40c to 85c, for silicon revision 2.0," on page 17 , and table 14, "current consumption for 0c to 70c, for silicon revision 2.0," on page 18 0 c min, 70 c max ?40 c min, 85 c max ?40 c min, 85 c max current consumption values table 13, "current consumption for ?40c to 85c, for silicon revision 2.0," on page 17 typical value changes for state retention, doze, and wait. see ta bl e . typical value changes for state retention, doze, and wait. see ta bl e . dpll maximum output freq range table 31, "dpll specifications," on page 37 mpll and spll = 532 mhz mpll and spll = 400 mhz
mcimx31/mcimx31l technical data, rev. 4.1 120 freescale semiconductor product documentation 7 product documentation this data sheet is labeled as a pa rticular type: product preview, adva nce information, or technical data. definitions of these types are avai lable at: http://www.freescale.com. mcimx31 product brief (order number mcimx31pb) mcimx31 reference manual (order number mcimx31rm) mcimx31 chip errata (order number mcimx31ce) the freescale manuals are available on th e freescale semiconducto rs web site at http://www.freescale.com/i mx. these documents may be download ed directly from the freescale web site, or printed versions may be ordered. arm ltd. documentation is available from http://www.arm.com. 8 revision history table 74 summarizes revisions to this document since the release of rev. 3.4. gpio maximum input current (100 k pu) table 15, "gpio dc electrical parameters," on page 22 v i = 0, i in = 25 a v i = nvcc, i in = 0.1 a n/a n/a core operating speed table 8, "operating ranges," on page 13 532 mhz 400 mhz package table 70, "ball map?14 x 14 0.5 mm pitch," on page 117 and table 71, "ball map?19 x 19 0.8 mm pitch," on page 118 mapbga packages 457 14 x 14 mm, 0.5 mm pitch 473 19 x 19 mm, 0.8 mm pitch mapbga package 47319x19mm, 0.8mm pitch pin assignment table 66, "14 x 14 bga signal id by ball grid location," on page 107 and table 69, "19 x 19 bga signal id by ball grid location," on page 113 mapbga packages 457 14 x 14 mm, 0.5 mm pitch 473 19 x 19 mm, 0.8 mm pitch mapbga package 47319x19mm, 0.8mm pitch table 74. revision history rev. location revision 4 figure 87 , ta bl e 7 3 updated. 4.1 table 1, "ordering information," on page 3 added note about jtag compliance. 4.1 section 1.2.1/3 updated with new operating frequencies 4.1 table 8, "operating ranges," on page 13 added new operating frequencies table 73. product differentiation (continued) item location mcimx31/mcimx31l mcimx31c/mcimx31lc
revision history mcimx31/mcimx31l technical data, rev. 4.1 freescale semiconductor 121 this page left intentionally blank
document number: mcimx31 rev. 4.1 11/2008 how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064, japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only : freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-521-6274 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circui ts or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpos e, nor does freescale semiconductor assume any liability arising out of the application or use of any product or ci rcuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor dat a sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. arm, arm thumb, jazelle, and the arm powered logo are registered trademarks of arm limited. arm1136jf-s, arm11, embedded trace kit, em bedded trace macrocell, etm, embedded trace buffer, and etb are trademarks of arm limited. al l other product or service names are the property of their respective owners. java and all other java-based marks are trademarks or registered trademarks of sun microsystems, inc. in the u.s. and other countries. france telecom ? tdf ? groupe des ecoles des telecommunic ations turbo codes patents license. ? freescale semiconductor, inc. 2005, 2006, 2007. all rights reserved.

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